Si MOS Capacitors Research Articles

Dose responses of the SiO2 used in radiation sensors in field effect transistor form

Aim: To investigate the structural changes in the SiO2 (silicon dioxide) layer, which is the sensitive region of the RadFET radiation sensors used in the medical field, and to elaborate the impacts of these modifications on electrical characteristics. Methods: Dry oxidation method was used to grow the SiO2 film on n-type Si (100) and SiO2 MOS capacitors were produced by using DC magnetron sputtering. Irradiation was carried out using a 60Co radioactive source at a dose range of 1 kGy-50 kGy. XRD (X-ray diffraction) results showed that no crystalline structure was formed in the studied dose range. Results: The results obtained from XPS (X-ray photoelectron spectroscopy) showed that Si-Si oxygen deficient bonds were formed in the post-production structure, resulting in the observation of flat band voltage ( ) at negative values. Conclusions: In general, the Si-Si oxygen deficient bond content increased with increasing radiation dose, causing the C-V curve to shift towards larger negative voltage values as desired. The device sensitivity was almost constant after 25 kGy.

Radiation-induced charge trapping in Si-MOS capacitors with HfO2/SiO2 gate dielectrics

The impact of high dose 60Co gamma-ray irradiation on the oxide traps and interface traps of Au/HfO2-SiO2/Si MOS capacitors is studied by C–V and G–V analysis. The results show that the trapped charges in oxide induce a shift in the C–V curves. The density of the oxide traps increases with the irradiation dose, following a linear relation below 20 kGy(SiO2) and a sublinear relation above that, and accordingly the effective trapping efficiency changes from 18.1% to 1.2%. The distribution of the interface trap density is affected by the irradiation dose. With the increase of the irradiation dose, the shallow energy level interface traps are more susceptible to be generated below 5 kGy(SiO2), but the discrepancy is largely diminished at the high dose of 500 kGy(SiO2). Fermi level pinning is observed at the high doses, and the Fermi level efficiency drops to 75.7% and 65.5% at 100 kGy(SiO2) and 500 kGy(SiO2), respectively.

The radiation response of hafnium oxide based metal-oxide-semiconductor capacitors under 60Co gamma ray

Radiation induced oxide and interface trapping characteristics in Al/HfO 2 /Si MOS capacitor under 60Co gamma ray are studied in this article. We discovered positive oxide trapped charge in the HfO 2 /Si system after gamma-irradiation with different total dose. Post-annealing process can reduce the radiation induced trapped charge density in the HfO 2 /Si system, and SiO 2 layer between HfO 2 and Si can greatly reduce the interface trapped charge density. Moreover, we discovered that oxygen vacancy is the dominant radiation induced defect in bulk HfO 2 , and silicon dangling bond and silicon suboxide are main interface defects related to the radiation induced interface trapping.

Experimental evidence of the existence of multiple charged states at Al2O3/GaN interfaces

The electrical properties of metal-oxide-semiconductor (MOS) capacitors with Al2O3/GaN interfaces formed by atomic layer deposition at various deposition temperatures (Td) were systematically investigated through comparison with the interface properties of a Si MOS capacitor. Although interface trap densities (Dit) for the GaN MOS capacitors are almost the same as for the Si MOS capacitor, surface potential fluctuation (σs) for the GaN MOS capacitors formed at various Td are much larger than for the Si MOS capacitor. Comparison between a theoretical calculation related to σs and the measured results clarified that the energy dependences of σs in the bandgap of GaN cannot be explained by electron trapping to the interface traps with the single acceptor nature (0/−). We found that the result is experimental evidence of the existence of multiple charge states at the Al2O3/GaN interfaces. The existence of multiple charge states suggests that it may be difficult to obtain good carrier transport in future GaN devices with a MOS structure.

Entirely relaxed lattice-mismatched GaSb/GaAs/Si(001) heterostructure grown via metalorganic chemical vapor deposition

A GaSb epilayer is grown on a GaAs/Si(001) epitaxial substrate via metalorganic chemical vapor deposition. High-resolution transmission electron microscopy micrographs and high-resolution X-ray reciprocal space mapping indicate an entirely relaxed interfacial misfit (IMF) array GaSb epilayer. The valence-band offset and conduction-band offset of the Al2O3/GaSb/GaAs/Si structure are estimated to be 2.39 and 3.65 eV, respectively. The fabricated Al2O3/p-GaSb/GaAs/Si MOS capacitors exhibited good capacitance–voltage characteristics with a small accumulation frequency dispersion of approximately 1.05% per decade. These results imply that the GaSb epilayer grown on the GaAs/Si platform in the IMF mode can be used for future complementary metal–oxide semiconductor applications.

Impacts of oxidants in atomic layer deposition method on Al2O3/GaN interface properties

The electrical interface properties of GaN metal–oxide–semiconductor (MOS) capacitors with an Al2O3 gate insulator formed by atomic layer deposition method using three kinds of oxidants were investigated by the capacitance–voltage technique, Terman method, and conductance method. We found that O3 and the alternate supply of H2O and O3 (AS-HO) are effective for reducing the interface trap density (Dit) at the energy range of 0.15 to 0.30 eV taking from the conduction band minimum. On the other hand, we found that surface potential fluctuation (σs) induced by interface charges for the AS-HO oxidant is much larger than that for a Si MOS capacitor with a SiO2 layer formed by chemical vapor deposition despite the small Dit values for the AS-HO oxidant compared with the Si MOS capacitor. This means that the total charged center density including the fixed charge density, charged slow trap density, and charged interface trap density for the GaN MOS capacitor is higher than that for the Si MOS capacitor. Therefore, σs has to be reduced to improve the performances and reliability of GaN devices with the Al2O3/GaN interfaces.

Demonstration of Large Flatband Voltage Shift by Designing Al2O3/SiO2 Laminated Structures with Multiple Interface Dipole Layers

We studied the dipole induced flatband voltage (VFB) shifts of Si MOS capacitors with Al2O3/SiO2/Al2O3/SiO2/Si laminated stacks ((Al2O3/SiO2) n /Si, n=2) designed for a large positive shift of VFB. The VFB shift caused by each dipole layer was determined from capacitance-voltage characteristics by excluding the effect of fixed charges. Due to the additivity of multiple dipole layers in the laminated stack, a large VFB shift (>1 V) was observed. In our experimental condition, the dipole layers at Al2O3-on-SiO2 interfaces were selectively formed, while those at SiO2-on-Al2O3 interfaces were effectively suppressed. The employed SiO2 deposition process was suggested to be one of the key parameters to determine the formation or suppression of interface dipole layer at SiO2-on-Al2O3 interface.

Design of Al2O3/SiO2 laminated stacks with multiple interface dipole layers to achieve large flatband voltage shifts of MOS capacitors

We studied the dipole induced flatband voltage (VFB) shifts of Si MOS capacitors with Al2O3/SiO2/Al2O3/SiO2/Si laminated stacks ((Al2O3/SiO2)n/Si, n = 2) designed for a large positive shift of VFB. The VFB shift caused by each dipole layer was determined from capacitance-voltage characteristics by excluding the effect of fixed charges. Due to the additivity of multiple dipole layers in the laminated stack, a large VFB shift (>1 V) was observed. In our experimental condition, the dipole layers at Al2O3-on-SiO2 interfaces were selectively formed, while those at SiO2-on-Al2O3 interfaces were effectively suppressed. The validity of such additivity of VFB shifts induced by selectively formed dipole layers was also experimentally demonstrated for n ≥ 3 laminated stacks. An introduction of multiple dipole layers is applicable for a threshold voltage tuning in a wider range than the tuning with a single dipole layer.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

Ta-Mo Isomorphous Alloy Systems for Metal Gate Apllications

Tantalum-molybdenum (Ta-Mo) thin films with various compositions are deposited on Si and HfO2/Si substrates by rf (radio frequency) magnetron sputtering. The isomorphous Ta-Mo thin film shows an amorphous structure with Mo/Ta rf power at 20/80 W. It is reported that an amorphous structure of gate electrodes can reduce threshold voltage variability among different devices, caused by different orientations of polycrystalline grains [1]. This amorphous layer may eliminate the effect for the fabrication of next generation CMOS devices. Different thicknesses of HfO2 dielectrics (20, 40, 60, 80, and 100 Å) are obtained by metal-organic chemical vapor deposition. The Ta-Mo thin films are deposited on HfO2/Si by cosputtering Ta and Mo targets. The composition of Ta-Mo alloys are controlled by varying the rf power (0/100, 20/80, 40/60, 60/40, 80/20, 100/0 W) on Ta and Mo targets. After that, a TaN layer is deposited on Ta-Mo layers to form a TaN/Ta-Mo/HfO2/Si MOS capacitor. The capacitor is further annealed at 400oC in a N2-H2 mixture for 30 min to study the thermal stability of the gate structure. The crystal structure is identified by grazing incident angle X-ray diffraction. Chemical bonding of Ta-Mo films is characterized by X-ray photoelectron spectroscopy. The resistivity is measured by using a four-point probe. Electrical properties of the MOS capacitors are characterized by capacitance–voltage (C-V) measurements. The work function is extracted from the C-V curves with different thicknesses of HfO2. The GIAXRD result suggests that the Ta and Mo phases appear for Ta-Mo films deposited with Mo/Ta rf power at 0/100 W and 100/0 W, respectively. Both of them are body-centered cubic (BCC) structures. For Ta-Mo thin films deposited with different Mo/Ta rf powers, the structures are also BCC structures, except for film deposited with Mo/Ta rf powers at 20/80 W. It exhibits an amorphous structure. In addition, the lattice constant decreases but the grain size increases as the rf power on Mo targets increases. The physical properties of Ta-Mo films and the effective work functions of the bilayer TaN/Ta-Mo gate electrodes will be addressed. [1] M. E. Grubbs, X. Zhang, M. Deal, Y. Nishi, and B. M. Clemens, Appl. Phys. Lett. 97, 223505 (2010). Figure 1

Electrical characterization of top-gated molybdenum disulfide metal–oxide–semiconductor capacitors with high-k dielectrics

Top-gated metal–oxide–semiconductor (MOS) capacitor test structures were fabricated with 30nm HfO2 and Al2O3 thin films by atomic layer deposition (ALD) on surface-functionalized, bulk molybdenum disulfide (MoS2), and characterized with C–V and I–V measurements. The C–V results showed significantly different behavior for MoS2 samples compared to conventional Si MOS capacitors, where the area dependence, frequency dependence, and hysteresis results demonstrate the possibility of different properties of high-k dielectrics on MoS2. The C–V frequency dispersion suggests the existence of defects in the interfacial region of the high-k/MoS2.

Study of electrical and micro-structural properties of high-κ gate dielectric stacks deposited using pulse laser deposition for MOS capacitor applications

The electrical properties of hafnium oxide (HfO2) gate dielectric as a metal–oxide–semiconductor (MOS) capacitor structure deposited using pulse laser deposition (PLD) technique at optimum substrate temperatures in an oxygen ambient gas are investigated. The film thickness and microstructure are examined using ellipsometer and atomic force microscope (AFM), respectively to see the effect of substrate temperatures on the device properties. The electrical J–V, C–V characteristics of the dielectric films are investigated employing Al–HfO2–Si MOS capacitor structure. The important parameters like leakage current density, flat-band voltage (Vfb) and oxide-charge density (Qox) for MOS capacitors are extracted and investigated for optimum substrate temperature. Further, electrical studies of these MOS capacitors have been carried out by incorporating La2O3 into HfO2 to fabricate HfO2/La2O3 dielectric stacks at an optimized substrate temperature of 800 °C using a PLD deposition technique under oxygen ambient. These Al–HfO2–La2O3–Si dielectric stacks MOS capacitor structure are found to possess better electrical properties than that of HfO2 based MOS capacitors using the PLD deposition technique.

Impact of interface trap density at metal/SiNx/n+ MOS capacitor in multilayered Si solar cells

Impact of the SiNx/n+-Si interface on silicon solar cell performance was investigated, where SiNx is used as a passivation layer. Significant shifts in capacitance, conductance and leakage current characteristics were observed for metal/SiN:H/n+-Si MOS capacitor when it was subjected to a constant voltage stress of +10 V at room temperature. The interface trap density (Dit) across the SiN:H/n+-Si interface increased from 6·3 × 109 to 7·5 × 109 cm−2eV−1 after a 500-s stress whereas the n+/p junction diode remained unaffected by the stress. A direct correlation between the degradation of SiN:H/Si interface and the solar cell performance was observed.

The Effects of Nitrogen Concentration in TiN<sub>x</sub> and the Thickness of HfSiO<sub>x</sub>N to the Tunneling Currents in Isotropic TiN<sub>x</sub>/HfSiO<sub>x</sub>N/SiO<sub>2</sub>/Si(100) Capacitors

In this paper, we have computed electron tunneling currents in TiNx/HfSiOxN/SiO2/Si (100) MOS capacitors by including a coupling term between transverse and longitudinal kinetic energies which is represented by an electron phase velocity in the gate. The effective mass of the substrate is considered as an isotropic mass. The transmittance was analytically calculated by employing an Airy-wavefunction approach, and the obtained transmittance was then utilized to calculate the tunneling current for different nitrogen compositions in the TiNx metal gate and the equivalent oxide thicknesses (EOTs) of HfSiOxN. It was shown that the tunneling current reduces considerably as the nitrogen composition of the TiNx metal gate decreases. It was also shown that the increase in the EOT reduces the tunneling current. In addition, the tunneling current shows an oscillatory behavior at high oxide voltages.

EFFECT OF GATE ELECTRODES ON STRUCTURE AND ELECTRICAL PROPERTIES OF SPUTTERED HfO2 THIN FILMS

High dielectric hafnium oxide films were grown by magnetron sputtering and post heat treatment in nitrogen atmosphere at 500°C for 30 min using vacuum annealing furnace. The film keeps amorphous at 500°C and has better interface quality as revealed by X-ray diffraction and transmission electron microscopy. The influence of TiN and Pt electrodes on the electrical property of the film was compared. For the annealed films, TiN electrode was presented as the optimal one. For the conduction mechanism of Pt / HfO 2/p- Si MOS capacitors under gate electron injection, the dominant conduction mechanism at low electric field is Schottky emission. At high electric field, the conversion of current transport mechanism from Schottky emission to trap-assisted tunneling for the annealed HfO 2 film occurs at 0.64 MV/cm.

Comparative Study ofSiO2,Al2O3, and BeO Ultrathin Interfacial Barrier Layers in Si Metal-Oxide-Semiconductor Devices

In a previous study, we have demonstrated that beryllium oxide (BeO) film grown by atomic layer deposition (ALD) on Si and III-V MOS devices has excellent electrical and physical characteristics. In this paper, we compare the electrical characteristics of inserting an ultrathin interfacial barrier layer such as SiO2, Al2O3, or BeO between the HfO2gate dielectric and Si substrate in metal oxide semiconductor capacitors (MOSCAPs) and n-channel inversion type metal oxide semiconductor field effect transistors (MOSFETs). Si MOSCAPs and MOSFETs with a BeO/HfO2gate stack exhibited high performance and reliability characteristics, including a 34% improvement in drive current, slightly better reduction in subthreshold swing, 42% increase in effective electron mobility at an electric field of 1 MV/cm, slightly low equivalent oxide thickness, less stress-induced flat-band voltage shift, less stress induced leakage current, and less interface charge.

Structural and electrical properties of Ta 2 O 5 thin films prepared by photo-induced CVD

Tantalum oxide (Ta 2 O 5 ) films and Al/Ta 2 O 5 /Si MOS capacitors were prepared at various powers by ultraviolet photo-inducing hot filament chemical vapour deposition (HFCVD). Effects of ultraviolet light powers on the structure and electrical properties of Ta 2 O 5 thin films were studied using X-ray diffraction (XRD) and atomic force microscopy (AFM). The dielectric constant, leakage current density and breakdown electric field of the samples were studied by the capacitance–voltage (C–V) and current–voltage (I–V) measurements of the Al/Ta 2 O 5 /Si MOS capacitors. Results show that the Ta 2 O 5 thin films grown without inducement of UV light belong to amorphous phase, whereas the samples grown with inducement of UV-light belong to δ-Ta 2 O 5 phase. The dielectric constant and leakage current density of the Ta 2 O 5 thin films increase with increasing powers of the UV- lamps. Effects of UV- lamp powers on the structural and electrical properties were discussed.

Investigation of the interface trap density and series resistance of a high-k HfO2-based MOS capacitor: before and after 50 MeV Li3+ ion irradiation

This is the first investigation on the effects of 50 MeV Li3+ ions on interface trap density (D it) and series resistance (R s), which reveal the improvement of the dielectric properties of RF-sputtered HfO2-metal oxide semiconductor (MOS) capacitors. The samples were irradiated and characterized at room temperature. The D it and R s were determined from the capacitance–voltage (C–V) and conduction–voltage (G–V) characteristics at 1 MHz. The measured capacitance and conductance were corrected for series resistance. It is found that the series resistance of Al/HfO2/p− Si MOS capacitors increases with ion fluence, calculated at a strong accumulation region before and after irradiation. The interface state density of MOS devices before and after irradiation is found to decrease with increasing ion fluence.

Trapping in GdSiO high-k films

In this article, the authors systematically characterized TiN/GdSiO/SiO2/Si metal oxide semiconductor capacitors from the point of view of charge trapping. Charge trapping was investigated measuring the flatband voltage with the pulsed capacitance-voltage (C-V) technique, in condition of injection from gate and substrate. As a result, a bell shaped curve of the flatband shift versus trapping time was found, with a turn-around at 100–200 μs. This was explained as the concomitant of transient phenomena due to a charge of opposite polarity starting from the two different interfaces of the high-k film. This study was possible only because of the pulsed C-V technique. At long times, trapping has always shown a logarithmic trend and the kinetics of trapping is linearly dependent on the applied voltage. Finally, dc and pulsed stress were performed at voltages of interest for logic applications.

Study of hafnium oxide deposited using Dense Plasma Focus machine for film structure and electrical properties as a MOS device

The electrical properties of HfO 2 gate dielectric as a MOS structure deposited using Dense Plasma Focus (DPF) device under different ambient gases were investigated. DPF is unique machine used for the first time to fabricate a MOS device as it can be used to deposit dielectric film in one shot and can also be used to change the properties of the thin film surface. The films were first deposited under pre-optimized conditions of DPF device to have best focus for producing ions. The substrate for deposition of dielectric material was placed at a distance of 5 cm from the focus under argon ambient and then under nitrogen ambient. The I– V, C– V characteristics of the dielectric film were investigated employing Al–HfO 2–Si MOS capacitor structure deposited using DPF. The MOS devices were studied to determine electrical parameters like breakdown voltage, oxide charges and leakage current deposited under two different gas ambient. The microstructure of thin film is examined by using AFM and the thickness of the film is examined using an ellipsometer. The reduction in surface roughness, shift in Flat-band voltage ( V fb) and reduction in oxide-charge density ( Q o x ) is seen maximum for MOS capacitor where HfO 2 as gate dielectric is deposited under nitrogen ambient using DPF machine.