Si Interface Passivation Layer Research Articles

Analysis of Low Dimensional Nanoscaled Inversion-Mode InGaAs MOSFETs for Next-Generation Electrical and Photonic Applications

The electrical characteristics of In0.53Ga0.47As MOSFET grown with Si interface passivation layer (IPL) and highkgate oxide HfO2layer have been investigated in detail. The influences of Si IPL thickness, gate oxide HfO2thickness, the doping depth, and concentration of source and drain layer on output and transfer characteristics of the MOSFET at fixed gate or drain voltages have been individually simulated and analyzed. The determination of the above parameters is suggested based on their effect on maximum drain current, leakage current, saturated voltage, and so forth. It is found that the channel length decreases with the increase of the maximum drain current and leakage current simultaneously. Short channel effects start to appear when the channel length is less than 0.9 μm and experience sudden sharp increases which make device performance degrade and reach their operating limits when the channel length is further lessened down to 0.5 μm. The results demonstrate the usefulness of short channel simulations for designs and optimization of next-generation electrical and photonic devices.

Reduction in interface state density of SiO2/Si-IPL/InP by fluorine and sulfur passivations

The characteristics of a liquid-phase-deposited SiO2 film on InP were investigated. The mixture of H2SiF6 and H3BO3 aqueous precursors was used as the growth solution. SiO2 on InP with (NH4)2S treatment showed good electrical characteristics owing to the reduction of native oxides and sulfur passivation. The electrical characteristics were further improved with an ultrathin Si interface passivation layer (IPL) through reductions in Fermi-level pinning and interface state density. Moreover, during the SiO2 deposition, the HF in the growth solution simultaneously and effectively removed native oxides from the Si-IPL and provided fluorine passivation on it. The Al/SiO2/Si-IPL/(NH4)2S-treated InP MOS capacitor showed superior electrical properties. The leakage current density reached 6.9 × 10−9 and 1.6 × 10−7 A/cm2 at ±2 V. The interface state density reached 3.6 × 1011 cm−2 eV−1 with low frequency dispersion of 12.3%.

Characteristics of liquid phase deposited SiO2 on (NH4)2S-treated GaAs with an ultrathin Si interface passivation layer

The characteristics of liquid-phase-deposited SiO2 film on GaAs were investigated. A mixture of H2SiF6 and H3BO3 aqueous precursors was used as the growth solution. SiO2 on GaAs with (NH4)2S treatment shows good electrical characteristics owing to the reduction of native oxides and sulfur passivation. The electrical characteristics are further improved with an ultrathin Si interface passivation layer (Si IPL) from the reduction of Fermi-level pinning and interface state density. Moreover, during the SiO2 deposition, HF in the growth solution can simultaneously and effectively remove native oxides on Si IPL and provide fluorine passivation on it. The Al/SiO2/Si IPL/(NH4)2S-treated GaAs MOS capacitor shows superior electrical properties. The leakage current densities can reach 7.4 × 10−9 and 6.83 × 10−8 A/cm2 at ±2 V. The interface state density can reach a 2.11 × 1011 cm−2 eV−1 with low frequency-dispersion of 8%.

Sputter-Deposited La2O3 on p-GaAs for Gate Dielectric Applications

The interfacial and electrical properties of RF sputtered La2O3 on p-GaAs substrates with and without ultrathin Si interface passivation layer (IPL) are reported. X-ray photoelectron spectroscopy (XPS) studies revealed the formation of thermally stable interfacial native oxide (Ga-oxide and As-oxide) for La2O3/Si/p-GaAs gate stacks. The presence of (La2O3)1-x(SiO2)x at the interface prevented the formation of La-hydroxide which improved the metal-oxide-semiconductor (MOS) device characteristics, such as interface state density (∼1.2×1012eV−1cm−2), frequency dispersion (∼7%), and hysteresis voltage (∼260 mV). A gate leakage current density of 1.1×10−5 A.cm−2 has been achieved at Vfb-1 V for an equivalent oxide thickness of 3.4 nm and small flat-band voltage instability under constant voltage stressing was observed. The electrical properties of Al/La2O3/Si/p-GaAs MOS capacitors were found to improve after post deposition annealing at 500°C.

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

A high performance In0.53Ga0.47As metal-oxide-semiconductor field effect transistor with silicon interface passivation layer

In this letter, we demonstrate a high performance In0.53Ga0.47As channel n-type metal-oxide-semiconductor field effect transistor with silicon interface passivation layer (IPL) and HfO2 gate oxide. Owing to the effectiveness of Si IPL on improving the interface quality, good device characteristics have been obtained, including the peak transconductance of 7.7 mS/mm (Lg=5 μm and Vd=50 mV), drive current of 158 mA/mm (Lg=5 μm, Vgs=Vth+2 V, and Vd=2.5 V), and the peak effective channel mobility of 1034 cm2/V s. As an important factor on device design, the impact of silicon IPL thickness on the transistor characteristics has been investigated.

CHALLENGES AND PROGRESS IN III-V MOSFETs FOR CMOS CIRCUITS

An overview of III-V MOSFET technological challenges in comparison to well-established heterostructure-based FET technologies is presented with an emphasis on required properties and possible solutions. Possible approaches to achieve thermodynamically stable high- k gate stack with low interface trap density are reviewed, followed with our results on amorphous Si interface passivation layer (IPL) in-situ deposited on top of GaAs or strained InGaAs MOSFET channels grown by molecular beam epitaxy. Main issues of Si IPL, namely increased equivalent oxide thickness due to IPL oxidation and Si diffusion into the semiconductor channel, are addressed using an in-situ deposited HfO 2 with ultrathin (down to 0.25 nm) Si IPL and controlling its bonding state at the interface. Enhancement mode inversion-type MOSFET with HfO 2 high- k oxide is demonstrated. The device employs amorphous Si interface passivation layer, sputter-deposited high- k oxide and metal TaN gate and modulation p-doped GaAs / AlGaAs heterostructure with inversion n -channel formed at the interface with the oxide. The MOSFET with equivalent oxide thickness of 3.7 nm and long 100 μm channel have maximum DC transonductance of 0.9 mS/mm, Ion/Ioff = 2×104 (at low Ioff of 30 nA) and effective channel mobility exceeding 1000 cm2/V-s at sheet electron density <2×1012 cm-2.

Self-aligned n-channel GaAs metal–oxide–semiconductor field-effect transistors (MOSFETs) using HfO 2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO 2/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm 2/V s) with high temperature PMA (950 °C, 1 min) and good inversion.

Influence of the substrate orientation on the electrical and material properties of GaAs metal-oxide-semiconductor capacitors and self-aligned transistors using HfO2 and silicon interface passivation layer

In this work, we studied the effects of postdeposition anneal (PDA) time and Si interface passivation layer on the material and electrical characteristics of the metal-oxide-semiconductor (MOS) capacitor with high-k (HfO2) material on different orientation substrates with (100), (110), and (311). The interfacial change of HfO2∕Si∕GaAs gate stacks after PDA has been characterized using x-ray photoelectron spectroscopy (XPS) and Dit measurement using conductance method and frequency dispersion. XPS measurement shows the formation of gallium and arsenic oxides with increasing annealing temperature. Unoxidized Si and gallium and arsenic oxides formation in the interface might act as traps. Self-aligned MOS field effect transistors using PDA at 600°C and post-metal-annealing at 800°C have also been fabricated and characterized. The (100) substrate has lower density of interface traps and higher mobility due to reduced Ga2O3 formation.

Self-aligned n-channel metal-oxide-semiconductor field effect transistor on high-indium-content In0.53Ga0.47As and InP using physical vapor deposition HfO2 and silicon interface passivation layer

In this work, we present the electrical and material characteristics of TaN∕HfO2∕In0.53Ga0.47As and InP substrate metal-oxide-semiconductor capacitors and self-aligned n-channel metal-oxide-semiconductor field effect transistor (n-MOSFET) with physical vapor deposition Si interface passivation layer. Excellent electrical characteristics, thin equivalent oxide thickness (∼1.7nm), and small frequency dispersion (<2%) were obtained. n-channel high-k InGaAs- and InP-MOSFETs with good transistor behavior and good split capacitance-voltage (C-V) characteristics on In0.53Ga0.47As and InP substrates have also been demonstrated.

Temperature effects of Si interface passivation layer deposition on high-k III-V metal-oxide-semiconductor characteristics

In this work, we studied the electrical characteristics of TaN∕HfO2∕GaAs metal-oxide-semiconductor capacitors with Si interface passivation layer (IPL) under various postdeposition anneal (PDA) conditions and various Si deposition temperatures/times. Using optimal Si IPL under reasonable PDA, post metal anneal conditions, and various Si deposition temperatures, excellent electrical characteristics with low frequency dispersion (<5%, and 50mV) and reasonable Dit value (∼1012eV−1cm−2) can be obtained. It was found that higher temperature of Si IPL deposition and longer PDA time at 600°C improved equivalent oxide thickness and leakage current.

Metal gate HfO2 metal-oxide-semiconductor structures on InGaAs substrate with varying Si interface passivation layer and postdeposition anneal condition

Recently, the authors have investigated the GaAs metal-oxide-semiconductor field-effect transistor using Si interface passivation layer (IPL) and HfO2 as gate dielectric. In this work, they have investigated InGaAs MOSCAP using the same oxide of HfO2 as gate insulator with Si IPL. In this work, the authors studied the effects of postdeposition anneal (PDA) time and Si IPL on the electrical characteristics of the metal-oxide-semiconductor capacitor with high-k (HfO2) material on InGaAs. Excellent electrical characteristics with thin equivalent oxide thickness (∼2.5nm), low frequency dispersion (<5%) have been obtained. The thickness of the Si IPL and PDA time were correlated with C-V characteristics.

MOSCAP's and MOSFET's on III-V Channel Materials with Si, Ge and SiGe Interface Passivation Layer

The electrical characteristics of TaN/HfO2/GaAs MOS capacitors with various interface passivation layers (Si, Ge and SiGe IPLs) under various PDA (post-deposition anneal), PMA (post-metal anneals) and process conditions are presented. High-k GaAs MOSFETs with reasonable electrical characteristics (i.e. thin EOT (< 2nm), low frequency dispersion (<5%) and peak mobility (1218 cm2/V-s) have been obtained.

MOSCAP's and MOSFET's on III-V Channel Materials with Si, Ge and SiGe Interface Passivation Layer

not Available.

High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon

To reduce density of interface states and avoid Fermi level pinning at the III–V-high-k interface we employed an amorphous Si interface passivation layer ( a-Si IPL) in situ deposited on top of GaAs or InGaAs MOSFET channels grown by molecular beam epitaxy. The high-k gate stack was further fabricated ex situ on top of the IPL with HfO 2 dielectric and TaN metal gate. Combination of transmission electron microscopy, X-ray photoelectron spectroscopy and capacitance–voltage methods was applied to the samples with various IPL thicknesses to study correlations of the interface structure and its chemistry with the formation/passivation of interface states. An unpinned Fermi level is demonstrated on both GaAs and InGaAs wafers when Si IPL is partially oxidized, corresponding to the minimum thickness of the a-Si IPL of 1.5 nm. Thermal stability of the gate stack up to 750 °C was demonstrated, making it appropriate for Si implant activation within MOSFET technology. Both depletion mode and enhancement mode n-channel MOSFETs were demonstrated with transconductance 0.27 mS/mm for 100 μm—long channel and channel electron mobility as high as 1100 cm 2/V s.

Metal-oxide-semiconductor capacitors on GaAs with high-k gate oxide and amorphous silicon interface passivation layer

We demonstrate the electrical properties of metal-oxide-semiconductor capacitors on molecular beam epitaxial GaAs in situ passivated with ultrathin amorphous Si (a-Si) layer and with ex situ deposited HfO2 gate oxide and TaN metal gate. Minimum thickness of the Si interface passivation layer of 1.5 nm is needed to prevent the Fermi level pinning and provide good capacitance-voltage characteristics with equivalent oxide thickness of 2.1 nm and leakage current of ⩽1.0mA∕cm2. Transmission electron microscopy analysis showed that the Si layer was oxidized up to 1.4 nm during ex situ processing while the interface between the GaAs and a-Si remained atomically sharp without any sign of interfacial reaction.