CHALLENGES AND PROGRESS IN III-V MOSFETs FOR CMOS CIRCUITS

Abstract

An overview of III-V MOSFET technological challenges in comparison to well-established heterostructure-based FET technologies is presented with an emphasis on required properties and possible solutions. Possible approaches to achieve thermodynamically stable high- k gate stack with low interface trap density are reviewed, followed with our results on amorphous Si interface passivation layer (IPL) in-situ deposited on top of GaAs or strained InGaAs MOSFET channels grown by molecular beam epitaxy. Main issues of Si IPL, namely increased equivalent oxide thickness due to IPL oxidation and Si diffusion into the semiconductor channel, are addressed using an in-situ deposited HfO 2 with ultrathin (down to 0.25 nm) Si IPL and controlling its bonding state at the interface. Enhancement mode inversion-type MOSFET with HfO 2 high- k oxide is demonstrated. The device employs amorphous Si interface passivation layer, sputter-deposited high- k oxide and metal TaN gate and modulation p-doped GaAs / AlGaAs heterostructure with inversion n -channel formed at the interface with the oxide. The MOSFET with equivalent oxide thickness of 3.7 nm and long 100 μm channel have maximum DC transonductance of 0.9 mS/mm, Ion/Ioff = 2×104 (at low Ioff of 30 nA) and effective channel mobility exceeding 1000 cm2/V-s at sheet electron density <2×1012 cm-2.