High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon

Abstract

To reduce density of interface states and avoid Fermi level pinning at the III–V-high-k interface we employed an amorphous Si interface passivation layer ( a-Si IPL) in situ deposited on top of GaAs or InGaAs MOSFET channels grown by molecular beam epitaxy. The high-k gate stack was further fabricated ex situ on top of the IPL with HfO 2 dielectric and TaN metal gate. Combination of transmission electron microscopy, X-ray photoelectron spectroscopy and capacitance–voltage methods was applied to the samples with various IPL thicknesses to study correlations of the interface structure and its chemistry with the formation/passivation of interface states. An unpinned Fermi level is demonstrated on both GaAs and InGaAs wafers when Si IPL is partially oxidized, corresponding to the minimum thickness of the a-Si IPL of 1.5 nm. Thermal stability of the gate stack up to 750 °C was demonstrated, making it appropriate for Si implant activation within MOSFET technology. Both depletion mode and enhancement mode n-channel MOSFETs were demonstrated with transconductance 0.27 mS/mm for 100 μm—long channel and channel electron mobility as high as 1100 cm 2/V s.