Charge Instability in High-k Gate Stacks with Metal and Polysilicon Electrodes

Abstract

Charge trapping in high-k transistor gate stacks shifts the threshold voltage and may affect the channel mobility. Since both electrons and holes may potentially contribute to charge trapping, it is important to determine the polarity of the trapped charge and to relate it to the stress or operating conditions. A constant-voltage stress was applied to nMOSFETs and pMOSFETs and the charge trapping in the gate stack and the interface trap generation was monitored by the DCIV method. Detailed band diagram for each stress condition is used to correlate the measured charge trapping and the interface trap generation/annihilation to the dominant tunneling current component and to delineate the physical mechanisms and charge-trapping pathways.