Si Gate Research Articles

Quality factor and digital inverter performance in gate underlap and overlap DMG FinFETs

This paper presents a comparative 3D simulation study of Quality factor among Gate Underlap and Overlap techniques in both Si and Ge Dual Material Gate (DMG) FinFETs using the Sentaurus TCAD tool. The results of both the techniques are carefully examined and compared with Conventional DMG FinFET to analyze the performances of these devices. The effect of gate overlap/underlap techniques on threshold voltage (Vth), ION/IOFF ratio, drain induced barrier lowering (DIBL), transconductance (gm), subthreshold swing (SS), and Quality factor (Q) are investigated. It is found that Ge DMG FinFETs have higher gm and quality factor values as compared to Si DMG FinFETs. The prospects of these techniques in low-power digital applications have been performed by implementing complementary Si DMG FinFET based inverter circuit. We have extracted the average delay and noise margin, where the overlap structure performs better such as high current gain and no overshoot/undershoot peaks in the transient characteristics.

A Study on the Electrical Characteristics of Synaptic Devices with Pt/Cr/HfO2/Pt/Cr/HfO2/SiO2/Si Gate Stacked Structures

A Study on the Electrical Characteristics of Synaptic Devices with Pt/Cr/HfO₂/Pt/Cr/HfO₂/SiO₂/Si Gate Stacked Structures

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Nanosheet gate-all-around devices have demonstrated several advantages in device performance and area scaling over finFET devices with higher device density and improved electrostatic control. Robust inner spacer (IS) and channel formation is critical for high performance, reduced variability and good yield. An isotropic dry etch of the sacrificial SiGe layer with extremely high selectivity to gate spacer, IS and Si channels is necessary for high-quality channel formation over a wide range of sheet widths. Furthermore, the nFET Si:P and pFET SiGe:B source-drain (S/D) epitaxy must be isolated using inner spacers or buffers to prevent damage during Channel Release (CR). The damage can be further mitigated with optimized CR etch chemistry, enabling IS scaling. We highlight S/D damage mechanisms during CR, then demonstrate reduced S/D damage by co-optimization of the IS, CR chemistry and S/D epitaxy.

Impact of Saturated Spontaneous Polarization on the Endurance Fatigue of Si FeFET With Metal/Ferroelectric/Interlayer/Si Gate Structure

Impact of Saturated Spontaneous Polarization on the Endurance Fatigue of Si FeFET With Metal/Ferroelectric/Interlayer/Si Gate Structure

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors (FeFETs) with metal/ferroelectric/interlayer/Si (MFIS) gate stack structure. In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect, we first establish a model to simulate the electron trapping behavior in n-type Si FeFET. The model is based on the quantum mechanical electron tunneling theory. And then, we use the pulsed I d–V g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET. Our model fits the experimental data well. By fitting the model with the experimental data, we get the following conclusions. (i) During the positive operation pulse, electrons in the Si substrate are mainly trapped at the interface between the ferroelectric (FE) layer and interlayer (IL) of the FeFET gate stack by inelastic trap-assisted tunneling. (ii) Based on our model, we can get the number of electrons trapped into the gate stack during the positive operation pulse. (iii) The model can be used to evaluate trap parameters, which will help us to further understand the fatigue mechanism of FeFET.

Fixed charges at the HfO[formula omitted]/SiO2 interface: Impact on the memory window of FeFET

In this article, the impact of interfacial fixed charges on the memory window (MW) of HfO2-based ferroelectric field-effect transistor (FeFET) is investigated using technology computer-aided design (TCAD) device simulations. We have considered the presence of fixed charges at the interface between the ferroelectric layer (FE) and the interlayer dielectric (IL) of FeFET with metal/ferroelectric/interlayer/Si (MFIS) gate structure. Our study indicates that the presence of fixed charges affects the polarization and corresponding depolarization field in the ferroelectric. Positive and negative interface charges can align the polarization direction. The MW degradation is observed with the increase in the fixed charge concentration (Qf).

Experimental investigation of time dependent dielectric breakdown and failure mechanism for Hf0.5Zr0.5O2 ferroelectric field effect transistors

The experimental investigation of the time dependent dielectric breakdown (TDDB) was performed to study the dielectric breakdown mechanisms for Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect transistors (FeFETs) with the SiO2 interfacial layer (IL). Constant voltage stress method combined with the TCAD device simulation was used to study the breakdown mechanism of the TaN/HZO/SiO2/Si gate stack. Due to the much higher electric field in the IL, the breakdown of the SiO2 IL is the major reason for the breakdown of the gate stack. In addition, it is found that the IL breakdown will speed up the disappearance of the memory window (MW), leading to the malfunction of the FeFET as a storage device. Finally, the Weibull distributions of time-to-breakdown (TBD) and charge-to-breakdown (QBD) were characterized, revealing decent TDDB performance of the FeFETs. Careful design of IL thickness is necessary to balance the tradeoff between the device performance and the reliability lifetime of HZO FeFETs.

Two-dimensional single crystal monoclinic gallium telluride on silicon substrate via transformation of epitaxial hexagonal phase

Van der Waals (vdW) epitaxial growth of large-area and stable two-dimensional (2D) materials of high structural quality on crystalline substrates is crucial for the development of novel device technologies. 2D gallium monochalcogenides with low in-plane symmetry stand out among the layered semiconductor materials family for next-generation optoelectronic and energy conversion applications. Here, we demonstrate the formation of large-area, single crystal and optically active 2D monoclinic gallium telluride (m-GaTe) on silicon substrate via rapid thermal annealing induced phase transformation of vdW epitaxial metastable hexagonal gallium telluride (h-GaTe). Stabilization of multilayer h-GaTe on Si occurs due to the role of the first layer symmetry together with efficient GaTe surface passivation. Moreover, we show that the phase transformation of h-GaTe to m-GaTe is accompanied by the strain relaxation between Si substrate and GaTe. This work opens the way to the fabrication of single-crystal 2D anisotropic semiconductors on standard crystalline wafers that are difficult to be obtained by epitaxial methods.

Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study

This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the channel and the narrow bandgap source. It shows an Ion of 392 μA/μm, an Ioff of 8.8 × 10−17 A/μm, an Ion/Ioff ratio of about 4.4 × 1012, and a minimum subthreshold slope of 9.3 mV/dec at Vd = 1 V. We also analyze the influence of the gate oxide and metal work functions on the transistor characteristics. A numerical device simulator, calibrated to the experimental data of a vertical InAs–Si gate all around TFET, is used to accurately predict different features of the device. Our simulations demonstrate that the proposed vertical TFET, as a fast-switching and very low power device, is a promising transistor for digital applications.

3 nm Channel MoS2 Transistors by Electromigration of Metal Interconnection

Further scaling down the feature size of transistors is central for the development of next-generation electronic devices. However, fabrication of transistors with channel lengths down to 5 nm has been challenging due to lithography limit and short channel effects (SCEs). Here, we demonstrate an MoS2-based device with the shortest 3 nm channel length among global back-gated transistors by feedback-controlled electromigration of metal interconnection. The Si/SiO2-back-gated model device shows on/off ratios of up to 2 × 105 and exhibits a field-effect mobility of up to 33.5 cm2 V–1 s–1, which is, to the best of our knowledge, the highest value in the as-yet-reported same-type transistors with a sub-10 nm channel length. This good immunity of the device to SCEs is also corroborated by the COMSOL Multiphysics simulation. After replacing the thicker physical gate SiO2 dielectric and Si electrode with the 2D hexagonal boron nitride (h-BN) and graphene monolayer, respectively, for better gate control, the field-effect mobility is pushed to 51.2 cm2 V–1 s–1 and displays excellent switching characteristics with near-ideal subthreshold swing of 67 mV dec–1 and drain-induced barrier lowering as low as 0.378 V V–1. This work can promote further transistor downscaling and extend Moore’s law.

Germanium Spherical Quantum-Dot Single-Hole Transistors With Self-Organized Tunnel Barriers and Self-Aligned Electrodes

We report the fabrication and electrical characterization of single-hole transistors (SHTs), in which a Ge spherical quantum dot (QD) weakly couples to self-aligned electrodes via self-organized tunnel barriers of Si3N4. A combination of lithographic patterning, sidewall spacers, and selfassembled growth was used for fabrication. The core experimental approach is based on the selective oxidation of poly-SiGe spacer islands located at the specially designed included-angle locations of Si3N4/Si-trenches. By adjusting processing times for conformal deposition, etch back and thermal oxidation, good tunability in the Ge QD size and its tunnel-barrier widths were controllably achieved. Each Ge QD is electrically addressable via self-aligned Si gate and reservoirs, thus offering an effective building block for implementing single-charge devices.

Low-Threshold pentacene OTFT by using NdTaON gate dielectric and ITO gate electrode

Ta-doped Nd oxynitrides (NdxTa(1-x)ON) are adopted as gate dielectrics in pentacene organic thin-film transistors on ITO glass for transparent applications. The device with Nd0.76Ta0.24ON can achieve the optimal performance with a high carrier mobility of 2.32 cm2/V·s and a small threshold voltage of −0.21 V. The capacitance–voltage results indicate that besides producing a high permittivity (high-k) for the gate dielectric, Ta incorporation in NdON can generate negative fixed charges in the oxide to assist the external gate voltage to produce a small threshold voltage. The threshold voltage is further reduced by the ITO gate electrode because ITO with higher work function can decrease the energy barrier for the charge-carrier injection at the source/channel interface. XPS and AFM reveal that the moisture resistance of pure Nd oxynitride can be enhanced by Ta doping to improve the smoothness of the dielectric surface, which results in weaker surface-roughness and grain-boundary scatterings, and consequently higher carrier mobility. The carrier mobility is further enhanced by the ITO gate electrode because similar to metal-gate/high-k stack, metallic ITO gate with higher electron concentration than Si gate can offer stronger screening effect on the carrier scattering induced by the severe atomic oscillation in the high-k NdTaON gate dielectric.

Defect Engineering in Thickness-Controlled Bi2O2Se-Based Transistors by Argon Plasma Treatment.

We present a simple, effective, and controllable method to uniformly thin down the thickness of as-exfoliated two-dimensional Bi2O2Se nanoflakes using Ar+ plasma treatment. Atomic force microscopy (AFM) images and Raman spectra indicate that the surface morphology and crystalline quality of etched Bi2O2Se nanoflakes remain almost unaffected. X-ray photoelectron spectra (XPS) indicate that the O and Se vacancies created during Ar+ plasma etching on the top surface of Bi2O2Se nanoflakes are passivated by forming an ultrathin oxide layer with UV O3 treatment. Moreover, a bottom-gate Bi2O2Se-based field-effect transistor (FET) was constructed to research the effect of thicknesses and defects on electronic properties. The on-current/off-current (Ion/Ioff) ratio of the Bi2O2Se FET increases with decreasing Bi2O2Se thickness and is further improved by UV O3 treatment. Eventually, the thickness-controlled Bi2O2Se FET achieves a high Ion/Ioff ratio of 6.0 × 104 and a high field-effect mobility of 5.7 cm2 V-1 s-1. Specifically, the variation trend of the Ion/Ioff ratio and the electronic transport properties for the bottom-gate Bi2O2Se-based FET are well described by a parallel resistor model (including bulk, channel, and defect resistance). Furthermore, the Ids-Vgs hysteresis and its inversion with UV irradiation were observed. The pulsed gate and drain voltage measurements were used to extract trap time constants and analyze the formation mechanism of different hysteresis. Before UV irradiation, the origin of clockwise hysteresis is attributed to the charge trapping/detrapping of defects at the Bi2O2Se/SiO2 interface and in the Bi2O2Se bulk. After UV irradiation, the large anticlockwise hysteresis is mainly due to the tunneling between deep-level oxygen defects in SiO2 and p++-Si gate, which implies the potential in nonvolatile memory.

Solar‐Blind Ultrathin Sn‐Doped Polycrystalline Ga2O3 UV Phototransistor for Normally Off Operation

Deep ultraviolet (DUV) photodetectors (PDs) based on ultrawide bandgap β‐Ga2O3 have great potential for aerospace, military, and civilian applications, especially because of their inherent solar blindness. An 8 nm thick Sn‐doped polycrystalline β‐Ga2O3 semiconductor is used as the channel material for a solar‐blind PD in this study. The β‐Ga2O3 channel is fully depleted by upward bending of the energy band owing to the work function difference between the highly p‐type Si (gate electrode) and β‐Ga2O3, resulting in normally off behavior with a positive threshold voltage under dark conditions. The normally off behavior is beneficial for simplicity of the gate‐driver circuitry and low power consumption under standby conditions. The fully depleted 8 nm thick polycrystalline β‐Ga2O3 exhibits high‐performance DUV detection capability of light at 215 nm: a low dark current of 29.3 pA and high photo‐to‐dark‐current ratio of ≈104 at zero gate voltage. This fully depleted n‐type β‐Ga2O3 semiconductor with a wafer‐scale substrate can expedite the realization of high‐performance and low‐power‐consumption solar‐blind PDs.

Experimental Extraction and Simulation of Charge Trapping During Endurance of FeFET With TiN/HfZrO/SiO2/Si (MFIS) Gate Structure

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window (MW) decreases: 1) the ferroelectric characteristic of Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is not degraded; 2) the trap density in the upper bandgap of the gate stacks increases; and 3) the reason for MW decrease is increased trapped electrons after program operation but not related to hole trapping/detrapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.

Improved carrier mobility of pentacene organic TFTs by suppressed oxide growth at remote interface using nitrogen doping in high-k NdNbO dielectric

Pentacene organic TFTs (OTFTs) using high-k Nd 2 O 3 doped with niobium and/or nitrogen as gate dielectric have been fabricated with gate-dielectric annealing at 200 °C and 400 °C. For 400 °C, the OTFT with only niobium doping in the Nd 2 O 3 gate dielectric shows an obvious improvement in carrier mobility compared with its counterpart with pure Nd 2 O 3 as gate dielectric. Moreover, for the lower temperature of 200 °C, the OTFT with both niobium and nitrogen dopings in the Nd 2 O 3 gate dielectric achieves further improvement with a small threshold voltage of −0.79 V and a high carrier mobility of 2.24 cm 2 /V·s. AFM and XPS reveal that the nitrogen doping, like the niobium doping, can reduce the hygroscopicity of Nd 2 O 3 , leading to a smoother surface of dielectric and thus larger overlying pentacene grains for reducing the scatterings of surface roughness and grain boundary respectively. Besides, highest mobility is achieved for the NdNbON gate dielectric without the best film quality because with nitrogen doping and lower-temperature annealing, a thinner interlayer between the gate dielectric and the Si gate is formed to enhance the electrostatic coupling between them, thus suppressing the phonon scattering on channel carriers caused by the thermal oscillation of the atoms inside the gate dielectric. •For pentacene OTFTs, Nb incorporation in Nd oxide as gate dielectric can reduce its hygroscopicity, leading to a smoother dielectric surface, larger pentacene grains, fewer interface traps and resultant improved performance. •Furthermore with N inclusion in NdNbO, high-performance OTFT can be achieved by using lower-temperature oxide annealing. •Besides passivation effect of nitrogen to further reduce hygroscopicity and oxygen vacancies, results show that nitrogen helps suppress formation of the dielectric/Si-gate interlayer, thus enhancing gate screening effect on the remote phonon scattering to improve carrier mobility.

Detection of individual spin species via frequency-modulated charge pumping.

We utilize a frequency-modulated charge pumping methodology to measure quickly and conveniently single "charge per cycle" in highly scaled Si/SiO2 metal-oxide-semiconductor field effect transistors. This is indicative of detection and manipulation of a single interface trap spin species located at the boundary between the SiO2 gate dielectric and Si substrate (almost certainly a Pb type center). This demonstration in sub-micrometer devices in which Dennard scaling of the gate oxide has yielded extremely large gate oxide leakage currents eliminates interference between the charge pumping current and the leakage phenomenon. The result is the ability to measure single trap charge pumping reliably and easily, which would otherwise be completely inaccessible due to oxide leakage. This work provides a unique and readily available avenue for single spin species detection and manipulation, which can be applied as a quantized standard of electrical current as well as to serve as a potentially useful platform for developing quantum engineering technologies. Finally, we discuss potential underlying physical mechanisms that are involved in producing a seemingly contradictory measure of both odd and even integer values for charge per cycle.

Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

Enhanced screening on remote phonon scattering in InGaZnO thin-film transistor by using Ge gate electrode

Room-temperature-processed amorphous InGaZnO thin-film transistors (TFTs) with three different semiconductors (Si, GaAs, and Ge) of various doping concentrations as gate electrodes are fabricated. Like the conventional Si gate devices, both their GaAs and Ge counterparts show carrier mobility increasing with increasing gate doping concentration, further supporting that the holes at/near the surface of a p-type gate electrode can have a screening effect on the remote phonon scattering caused by the surface phonons of their high-k gate dielectrics. Moreover, for the same gate doping concentration, the Ge gate device has a carrier mobility about three times that of its conventional Si gate counterpart. This implies that lower-mass charge carriers in the gate electrode could have a stronger screening effect on remote phonon scattering. As a result, even with a moderate gate doping concentration of 1.0 × 1018 cm−3, the room-temperature-processed Ge gate device shows a high carrier mobility of 60.8 cm2/V s. The enhanced screening effect of the Ge gate electrode should be due to its higher-energy plasmons, which could couple more strongly with the phonons of the gate dielectric to result in weaker gate-dielectric vibration.

Reliability Analysis on TiN Gated NMOS Transistors

Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.