The authors report on the effects of elevated ambient and substrate temperatures (25-500/spl deg/C) on the electrical characteristics of 6H polytype silicon carbide (SiC) MOSFETs. The work focuses primarily on modelling the temperature variations of the large- and small-signal parameters of the devices with a view to assessing their suitability for high-temperature integrated electronics. These parameters include threshold voltages, leakage currents, body-bias effects, and small-signal transconductances and output conductances. Where relevant, the authors' results are compared to silicon MOSFETs and GaAs MESFETs. Above 225/spl deg/C, the parameter variations of their SiC MOSFETs, including the observation of zero temperature coefficient (ZTC) drain currents, are qualitatively similar to those of Si MOSFETs and of GaAs MESFETs. In contrast with silicon MOSFETs. However, the gate transconductance (g/sub m/) and the channel mobility (/spl mu/) increase with increasing temperature up to 225/spl deg/C approximately because of a high interface state density. The ON/OFF current ratio of their SIC MOSFETs is at least two orders of magnitude higher than for Si and GaAs FETs above 200/spl deg/C. Junction leakage current densities measured up to 500/spl deg/C are several orders of magnitude lower than in high quality Si and GaAs devices, as expected from the higher bandgap energy for their SiC material (/spl ap/3 eV). While the junctions retained their electrical integrity, their MOSFETs displayed large gate-to-drain leakage currents above 300/spl deg/C, apparently due to an oxide reliability problem. Pin-to-pin package leakage is also observed above the same temperature. Despite this partial form of damage, the authors believe that their results confirm the expected potential of SIC MOSFETs for integrated circuit applications above 250/spl deg/C. The data reported in the paper, for this novel SIC process, are used to derive MOSFET models and SPICE parameters for analogue IC design, and an NMOS operational amplifier (OPAMP) is presented which is expected to operate in the range 25/spl deg/C to 500/spl deg/C, where silicon and GaAs technologies are unsuitable.