High resolution electron beam and dry etch based process for self-aligned 200 nm Si FET’s

Abstract

A high resolution fabrication process for integrated semiconductor structures with 100 nm minimum feature sizes, based on electron beam lithography and reactive ion etching, will be described. This process has been used in the fabrication of self‐aligned Si FET’s. Both single and multilayer resist structures have been employed. SiO2 sidewall spacers and As+ ion implantation allows for minimum source‐to‐gate and drain‐to‐gate spacings of 100 nm. Channel depths between 40 and 80 nm have been reached with double ion implantation and low temperature‐time cycles. Si MESFET and buried channel MOSFET devices and circuits have been fabricated in order to evaluate the capabilities of this process. The obtained switching speed for normally‐off Si MESFET logic is superior to any previously reported result for Si MESFET’s. Ultimate limits of this process and its implications on device performance are also addressed.