Si Complementary Metal Oxide Semiconductor Research Articles

Carbon based nanoelectronics: Materials and devices

The foundation for modern information technology (IT) is integrated circuits chips, and more than 90% of the chips are composed of devices fabricated using complementary metal-oxide-semiconductor (CMOS) nanotechnology. After miraculous developments of five decades, Si CMOS is moving into 14 nm node, and will arrive at its absolute performance limit before 2020. And research on nanoelectronics beyond 2020 is urgently needed. It now becomes a generally accepted fact that we may have to face the possibility of giving up silicon when come to 8 nm technology node, and nanoelectronics using non-Si materials may shake the very foundation of the semiconductor and IT industry. Among the few options being considered, carbon based nanoelectronics, including those using carbon nanotube (CNT) and graphene, are regarded being most promising. Recent developments in Peking University suggest that in 14 nm technology node, CNT based transistors outperform that of Si devices by about 10 times both in terms of speed and power dissipation, and it will become ever more advantageous when scaled further down to sub-10 nm regime.

Stability of Pseudomorphic and Compressively Strained Ge1-XSnx Thin Films under Rapid Thermal Annealing

Silicon lacks the higher mobility and direct band gap needed for faster electronics or active photonic applications. This shortcoming has pushed research towards the incorporation of other material systems, such as Ge1-xSnx, for increased mobility and possible direct band gap. Increasing the mole fraction of Sn will eventually lead to an indirect-to-direct crossover around 9 % Sn [1]. Additionally, the growth temperatures and processing steps for Ge1-xSnxfilms are backend Si complementary metal oxide semiconductor (CMOS) compatible.The challenges facing Ge1-xSnx grown by the chemical vapor deposition (CVD) technique are limitations of the Sn gaseous precursors. The deuterated stannane (SnD4) precursor has demonstrated monolithic growth of Ge1-xSnx directly on Si, but this gas is unstable at room temperature and can decompose within days. A more commercially accessible and stable precursor, stannic chloride (SnCl4), is stable under standard room temperature storage. Its role in Ge1-xSnx growth has started to be incorporated using commercially available CVD reactors [2]. However, an initial Ge buffer layer grown on Si prior to the Ge1-xSnx film is needed to mediate the Si-Cl reactivity. The lattice mismatch at the Ge1-xSnx/Ge interface is reduced compared to Si, which allows compressively strained and pseudomorphic Ge1-xSnxthin films to be grown.The growth of Ge1-xSnx thin films on Ge is done at temperatures below 400 °C; however Sn inter-diffusion between the Ge1-xSnx and Ge buffer layer during high temperature processing steps presents an unknown for future device reliability. This inter-diffusion of Sn between growth layers was observed already for a 500 °C, 30 minute anneal of Ge1-xSnx/Ge/Si [2]. Other post-growth annealing studies of the thermal stability of thin film Ge1-xSnx/Ge have focused only on single Sn mole fractions and thin films strained below the critical thickness [3-5]. Future applications in Si optoelectronics will require a more detailed study of thicker Ge1-xSnx layers and of multiple Sn mole fractions. In this paper, we investigate on the post-growth RTA stability of Ge1-xSnx/Ge/Si thin films grown with six different Sn mole fractions from 0.009 to 0.07. The Sn mole fraction and film thicknesses are listed in Table 1. The Ge1-xSnx thin films were grown partially pseudomorphic on a Ge buffer layer using an ASM Epsilon®reduced pressured CVD reactor. The lattice constants measured for each sample using X-ray diffraction rocking curves in Fig. 1 show a decrease in strain percentage at increased temperatures. Atomic force microscopy measured the film surface roughness change from a cross-hatched on the as-grown, to clumps of Sn-segregates for samples subjected to high temperature RTA. The samples that were observed to be relaxed as measured by XRD, also showed an increased red-shift for the Ge-Ge LO phonon measured by Raman spectroscopy. This red-shift indicates a higher incorporation of Sn atoms in the lattice for those annealed samples. Room temperature photoluminescence (PL) spectra indicate initial film degradation for short time anneals at constant temperature, but increased time shows film quality improvements [Fig. 2]. An increase in the PL emission intensity points to a reduced number of non-radiative traps.Table I. Ge1-xSnxsample compositions and thicknessSn mole fractionGe1-xSnx thickness (nm)0.0093270.0262570.0271730.032760.0321280.06450.07211 1. G. Grzybowski, et al., Appl. Phys. Lett. 101, 072105 (2012).2. B. Vincent, et al., Appl. Phys. Lett. 99, 152103 (2011).3. M.-Y. Ryu, et al., Appl. Phys. Lett. 102, 171908 (2013).4. H. Li, et al., Appl. Phys. Lett. 102, 251907 (2013).5. R. Chen, et al., J. of Crystal Growth 365, 29-34 (2013).

Monolithically Integrated Ge-on-Si Active Photonics

Monolithically integrated, active photonic devices on Si are key components in Si-based large-scale electronic-photonic integration for future generations of high-performance, low-power computation and communication systems. Ge has become an interesting candidate for active photonic devices in Si photonics due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS) processing. In this paper, we present a review of the recent progress in Ge-on-Si active photonics materials and devices for photon detection, modulation, and generation. We first discuss the band engineering of Ge using tensile strain, n-type doping, Sn alloying, and separate confinement of Γ vs. L electrons in quantum well (QW) structures to transform the material towards a direct band gap semiconductor for enhancing optoelectronic properties. We then give a brief overview of epitaxial Ge-on-Si materials growth, followed by a summary of recent investigations towards low-temperature, direct growth of high crystallinity Ge and GeSn alloys on dielectric layers for 3D photonic integration. Finally, we review the most recent studies on waveguide-integrated Ge-on-Si photodetectors (PDs), electroabsorption modulators (EAMs), and laser diodes (LDs), and suggest possible future research directions for large-scale monolithic electronic-photonic integrated circuits on a Si platform.

Temperature dependent spectral response and detectivity of GeSn photoconductors on silicon for short wave infrared detection.

The GeSn direct gap material system, with Si complementary-metal-oxide semiconductor (CMOS) compatibility, presents a promising solution for direct incorporation of focal plane arrays with short wave infrared detection on Si. A temperature dependence study of GeSn photoconductors with 0.9, 3.2, and 7.0% Sn was conducted using both electrical and optical characterizations from 300 to 77 K. The GeSn layers were grown on Si substrates using a commercially available chemical vapor deposition reactor in a Si CMOS compatible process. Carrier activation energies due to ionization and trap states are extracted from the temperature dependent dark I-V characteristics. The temperature dependent spectral response of each photoconductor was measured, and a maximum long wavelength response to 2.1 μm was observed for the 7.0% Sn sample. The DC responsivity measured at 1.55 μm showed around two orders of magnitude improvement at reduced temperatures for all samples compared to room temperature measurements. The noise current and temperature dependent specific detectivity (D*) were also measured for each sample at 1.55 μm, and a maximum D* value of 1 × 10(9) cm·√Hz/W was observed at 77 K.

Challenges of contact module integration for GaN-based devices in a Si-CMOS environment

The authors report on the integration of an Au-free contact module intended for AlGaN/GaN high-electron-mobility transistors fabricated in a 200 mm Si complementary metal–oxide–semiconductor facility. Contacts are characterized via transfer line method structures, tunneling electron microscopy, and energy-dispersive x-ray spectroscopy. Factors leading to incorrect extraction of contact resistance are discussed. The authors find that reoptimization of chemical vapor deposited silicon nitride on AlGaN/GaN substrates is required to ensure reliable determination of contact resistance, gate-to-source spacing, and gate-to-drain spacing. Additional process development is required to enable parallel processing of Si and GaN devices.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

High power and widely tunable Si hybrid external-cavity laser for power efficient Si photonics WDM links

A highly efficient silicon (Si) hybrid external cavity laser with a wavelength tunable ring reflector is fabricated on a complementary metal-oxide semiconductor (CMOS)-compatible Si-on-insulator (SOI) platform and experimental results with high output power are demonstrated. A III-V semiconductor gain chip is edge-coupled into a SOI cavity chip through a SiN(x) spot size converter and Si grating couplers are incorporated to enable wafer-scale characterization. The laser output power reaches 20 mW and the highest wall-plug efficiency of 7.8% is measured at 17.3 mW in un-cooled condition. The laser wavelength tuning ranges are 8 nm for the single ring reflector cavity and 35 nm for the vernier ring reflector cavity, respectively. The Si hybrid laser is a promising light source for energy-efficient Si CMOS photonic links.

Material Characterization of Ge1−x Sn x Alloys Grown by a Commercial CVD System for Optoelectronic Device Applications

High-quality compressive-strained Ge1−xSnx/Ge films have been deposited on Si(001) substrate using a mainstream commercial chemical vapor deposition reactor. The growth temperature was kept below 450°C to be compatible with Si complementary metal–oxide–semiconductor processes. Germanium tin (Ge1−xSnx) layers were grown with different Sn composition ranging from 0.9% to 7%. Material characterizations, such as secondary-ion mass spectrometry, Rutherford backscattering spectrometry, and x-ray diffraction analysis, show stable Sn incorporation in the Ge lattice. Comparison of the Sn mole fractions obtained using these methods shows that the bowing factor of 0.166 nm (in Vegard’s law) is in close agreement with other experimental data. High-resolution transmission electron microscopy and atomic force microscopy results show that the films have started to relax through the formation of misfit and threading dislocations. Raman spectroscopy, ellipsometry, and photoluminescence (PL) techniques are used to study the structural and optical properties of the films. Room-temperature PL of the films shows that 7% Sn incorporation in the Ge lattice results in a decrease in the direct bandgap of Ge from 0.8 eV to 0.56 eV.

Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator

In this paper, we present a fractionally injection-locked frequency multiplication technique that can solve the tradeoff between the selectable frequency step and phase noise of injection-locked frequency multipliers (ILFMs). For a given output frequency step, the phase noise of the proposed ILFM is lower than that of conventional ILFMs because higher-frequency signals can be injected. The proposed ILFM was fabricated using a 180 nm Si complementary metal oxide semiconductor (CMOS) process. 1/2-, 1/3-, 1/4-, and 1/6-integral frequency multiplications were realized, which means that the output frequency resolution is 6 times as high as that of conventional ILFM. When the reference frequency was 100 MHz, the measured phase noise at 725 (= 100×29/4) MHz was -120 dBc/Hz at a 1 MHz offset, and that at 767 (= 100×23/3) MHz was -119 dBc/Hz at 1 MHz offset.

Strain analysis in SiN/Ge microstructures obtained via Si-complementary metal oxide semiconductor compatible approach

We have analyzed the strain distribution and the photoluminescence in Ge microstructures fabricated by means of a Si-CMOS compatible method. The tensile strain in the Ge microstructures is obtained by using a SiN stressor layer. Different shapes of microstructure, allowing the Ge layers to freely expand into one, two, or three dimensions, resulted in different strain distribution profiles. Maximal equivalent biaxial tensile strain values up to ∼0.8% have been measured. Room temperature photoluminescence emission has been observed and attributed to direct-band gap recombination spectrally shifted by tensile strain.

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS) friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar integration of III-V and Si CMOS devices in a common fabrication infrastructure. A method of making ohmic contacts to buried III-V films using silicide metallurgies has been established. NiSi/Si/III-V dual heterojunction contact structures are found to be optimal for integration. These structures allow contact resistivities to be controlled by Si/III-V interfaces and eliminate interactions between the buried III-V device and metal layers. Using a modified transmission line method (TLM) test structure fabricated using standard CMOS processing techniques, the specific contact resistivities of Si/GaAs and Si/InxGa1-xAs interfaces are extracted. The relationship between specific contact resistivity and heterojuntion barrier width is considered. Among the structures tested in this work, p-type Si/GaAs and n-type Si/InxGa1-xAs yielded the lowest contact resistivities. Using the p-type Si/GaAs interface, a GaAs/AlxGa1-xAs laser with NiSi top contact is demonstrated, confirming the feasibility of NiSi/Si/III-V contact structures for III-V devices.

Monolithic Ge-on-Si lasers for large-scale electronic–photonic integration

A silicon-based monolithic laser source has long been envisioned as a key enabling component for large-scale electronic–photonic integration in future generations of high-performance computation and communication systems. In this paper we present a comprehensive review on the development of monolithic Ge-on-Si lasers for this application. Starting with a historical review of light emission from the direct gap transition of Ge dating back to the 1960s, we focus on the rapid progress in band-engineered Ge-on-Si lasers in the past five years after a nearly 30-year gap in this research field. Ge has become an interesting candidate for active devices in Si photonics in the past decade due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS) processing. In 2007, we proposed combing tensile strain with n-type doping to compensate the energy difference between the direct and indirect band gap of Ge, thereby achieving net optical gain for CMOS-compatible diode lasers. Here we systematically present theoretical modeling, material growth methods, spontaneous emission, optical gain, and lasing under optical and electrical pumping from band-engineered Ge-on-Si, culminated by recently demonstrated electrically pumped Ge-on-Si lasers with >1 mW output in the communication wavelength window of 1500–1700 nm. The broad gain spectrum enables on-chip wavelength division multiplexing. A unique feature of band-engineered pseudo-direct gap Ge light emitters is that the emission intensity increases with temperature, exactly opposite to conventional direct gap semiconductor light-emitting devices. This extraordinary thermal anti-quenching behavior greatly facilitates monolithic integration on Si microchips where temperatures can reach up to 80 °C during operation. The same band-engineering approach can be extended to other pseudo-direct gap semiconductors, allowing us to achieve efficient light emission at wavelengths previously considered inaccessible.

1.2–17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor

A wide-frequency-range phase-locked loop (PLL) with subharmonic injection locking is proposed. The PLL is equipped with a wide tunable ring-type voltage-controlled oscillator (ring VCO), frequency dividers, and a doubler in order to the widen injection-locked tuning range (ILTR). In addition, high-frequency injection signals are used to improve phase noise, which is supposed to be generated by a reference PLL. The proposed circuit is fabricated by using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. The measured frequency tuning range is from 1.2 to 17.6 GHz with a frequency doubler and dividers. The phase noise at 14.4 GHz (=32×450 MHz) with injection locking was -109 dBc/Hz, which shows a 21-dB reduction compared with that in the case without injection locking.

Electro-absorption modulation in horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguides

An ultracompact, broadband, and fully complementary metal-oxide-semiconductor (CMOS) compatible Si nanoplasmonic electro-absorption modulator is proposed based on the recently developed horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguide. The modulation relies on a highly accumulated electron layer at the insulator/Si interface induced by an applied voltage. Proof-of-concept devices are fabricated using standard Si CMOS technology. A 3-dB modulation around 1550 nm is measured under ∼6.5 V bias for a device with total length of only 4 μm. The design suggests that larger modulation could be achieved by using high-κ dielectrics as the insulator, thinning down the insulator thickness, and narrowing the Si core of the nanoplasmonic waveguide.

III-Nitride full-scale high-resolution microdisplays

We report the realization and properties of a high-resolution solid-state self-emissive microdisplay based on III-nitride semiconductor micro-size light emitting diodes (µLEDs) capable of delivering video graphics images. The luminance level of III-nitride microdisplays is several orders of magnitude higher than those of liquid crystal and organic-LED displays. The pixel emission intensity was almost constant over an operational temperature range from 100 to −100 °C. The outstanding performance is a direct attribute of III-nitride semiconductors. An energy efficient active drive scheme is accomplished by hybrid integration between µLED arrays and Si CMOS (complementary metal–oxide–semiconductor) active matrix integrated circuits. These integrated devices could play important roles in emerging fields such as biophotonics and optogenetics, as well as ultra-portable products such as next generation pico-projectors.

Ge 1−xSn x stressors for strained-Ge CMOS

In this paper, we propose the fabrication of whole strained Ge complementary metal–oxide-semiconductor (CMOS) with Ge 1− x Sn x materials as stressors to outperform the state-of-the-art uniaxial compressive strained Si CMOS. Ge 1− x Sn x materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Firstly, we have demonstrated p-type doped Ge 1− x Sn x growth by using either B implantation or in situ Ga doping technique. In the B-implanted Ge 1− x Sn x formation case, fully strained B-doped Ge 1− x Sn x layers with no Sn precipitation can be obtained even after solid phase epitaxial regrowth (SPER). However, the serious dislocation generation in the layer was occurred during SPER. This is caused by the point defects introduced by B implantation. In order to avoid this crystal damage, we have also demonstrated in situ Ga-doped Ge 1− x Sn x growth. In this case, we can achieve fully strained Ga-doped Ge 1− x Sn x growth without Sn precipitation and any defect generation. Secondary, we have demonstrated the formation of Ni(Ge 1− y Sn y ) layers for metal/semiconductor contact and investigated the crystalline qualities. The formation of polycrystalline Ni(Ge 1− y Sn y ) layers on Ge 1− x Sn x layers with Sn contents ranging from 2.0% to 6.5% after annealing at from 350 °C to 550 °C can be achieved. Additionally, in the case of the Ni/Ge 1− x Sn x /Ge sample with a Sn content of 3.5%, an epitaxial Ni 2(Ge 1− y Sn y ) layer on a Ge 1− x Sn x layer was formed. However, the surface roughness due to the agglomeration of Ni(Ge 1− x Sn x ) increases with increasing the Sn content and the annealing temperature. Therefore, a low thermal budget must be required for the formation of Ni(Ge 1− x Sn x ) with high Sn content.

On the role of Ti adlayers for resistive switching in HfO2-based metal-insulator-metal structures: Top versus bottom electrode integration

The authors demonstrate bipolar resistive switching in TiN/HfO2/Ti(top)/TiN devices using a (Bi) complementary metal-oxide semiconductor (CMOS) compatible technology process. The device performance includes a cycling endurance in dc sweeping mode >103. The results suggest that HfO2-based metal-insulator-metal devices with Si CMOS compatible metal electrodes may be well suited for future embedded nonvolatile memory applications. However, hysteretic current-voltage characteristics were only observed for a Ti top adlayer, whereas a Ti bottom adlayer integration did not show any resistive switching effect. Using x-ray photoelectron spectroscopy, the authors examined the interface chemistry of the Ti/HfO2 interface. It is clearly observed that Ti top adlayer deposition results in an increased nitrogen- and oxygen-gettering activity in contrast to Ti bottom adlayer. It follows that the formation of a nonstoichiometric HfO2 layer at the Ti/HfO2 interface is crucial for resistive switching.

Facet-embedded thin-film III–V edge-emitting lasers integrated with SU-8 waveguides on silicon

A thin-film InGaAs/GaAs edge-emitting single-quantum-well laser has been integrated with a tapered multimode SU-8 waveguide onto an Si substrate. The SU-8 waveguide is passively aligned to the laser using mask-based photolithography, mimicking electrical interconnection in Si complementary metal-oxide semiconductor, and overlaps one facet of the thin-film laser for coupling power from the laser to the waveguide. Injected threshold current densities of 260A/cm(2) are measured with the reduced reflectivity of the embedded laser facet while improving single mode coupling efficiency, which is theoretically simulated to be 77%.

(Invited) Assessment of Ge1-xSnx Alloys for Strained Ge CMOS Devices

In this paper, we propose the fabrication of whole strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1-xSnx materials as embedded stressors to outperform the state-of-the-art strained Si CMOS. Ge1-xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Compatibility of Ge1-xSnx (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation, in situ Ga doping, and Ni(Ge1-ySny) formation) is characterized. A low thermal budget has been determined for those processes on Ge1-xSnx alloys: temperatures must be lower than 600{degree sign}C for B activation and lower than 450{degree sign}C for Ni(Ge1-ySny) formation.

Ge-on-Si laser operating at room temperature

Monolithic lasers on Si are ideal for high-volume and large-scale electronic-photonic integration. Ge is an interesting candidate owing to its pseudodirect gap properties and compatibility with Si complementary metal oxide semiconductor technology. Recently we have demonstrated room-temperature photoluminescence, electroluminescence, and optical gain from the direct gap transition of band-engineered Ge-on-Si using tensile strain and n-type doping. Here we report what we believe to be the first experimental observation of lasing from the direct gap transition of Ge-on-Si at room temperature using an edge-emitting waveguide device. The emission exhibited a gain spectrum of 1590-1610 nm, line narrowing and polarization evolution from a mixed TE/TM to predominantly TE with increasing gain, and a clear threshold behavior.