Si CMOS Research Articles

(Invited) Flexible GHz Frequency and Low-Power Nanoelectronics Based on 2D Nanomaterials

2014 is the 10th year anniversary of the groundbreaking work on graphene by several pioneering workers. Since then, the field has expanded exponentially and now includes two-dimensional (2D) atomic sheets beyond graphene such as hexagonal boron nitride (hBN), transition metal dichalcogenides (TMDs), and group IV elemental monolayers (e.g. silicene, germanene). While there are many opportunities for these 2D crystals to enable transformational impact, it is widely understood that their greatest prospects are for flexible nanoelectronics where their combined synergistic properties are unmatched by conventional organic or inorganic materials. The 2D atomic sheets have emerged as near ideal nanomaterials to overcome the long running challenge of achieving Si CMOS like performance on soft substrates at scales that can be suitable for large integration. For instance, the high mobility and velocity accessible in monolayer graphene affords GHz analog transistor devices while the large bandgap of graphene’s semiconducting analogues (MoS2 and similar dichalcogenides) naturally lead to near ideal digital transistors with high on/off current ratio and low subthreshold slope while sustaining mobilities much larger than organic semiconductors or amourphous bulk semiconductors. Together, these physically similar atomic layers with vastly different electronic properties can serve as the electronic platform for low-power digital, high-speed mixed-signal, and high-frequency analog transistor building blocks for flexible nanoelectronic systems.In this work, we present the latest findings on the high frequency properties of graphene with record frequencies in the microwave regime. These high frequencies are suitable for realizing GHz wireless analog circuits on soft substrates. The current frequencies are limited by the poor thermal conductivity and reliability of the plastic substrates. In addition, we report on the coupled device mechanics and device physics of 2D semiconducting sheets. The device mechanics on plastic substrate as a function of tensile strain reveal that dielectric cracking is responsible for off-current degradation while buckling is largely responsible for on-current degradation. The buckling scales with the thickness of the dichalcogenide semiconductor and can be mitigated by reducing the driving force for delamination. Optimized dielectric patterning for strain relaxation was found to improve device reliability at low bending radius. Our results collectively indicate that graphene is the most suitable material for flexible radio-frequency transistors while TMDs are ideal for low-power flexible transistors.

Fano Resonance Photonic Crystal Membrane Lasers and Filters for Integrated Silicon Photonics

Fano resonance, known from atomic physics, has been employed for a wide variety of nanophotonic structures, such as quantum dots, photonic crystal, plasmonics, and metamaterials, and so on. With modal dispersion engineering, Fano filters and reflectors can all be realized in single layer dielectric photonic crystal structures. Based on Fano resonance principle in 2D air hole photonic crystal slabs, combined with crystalline semiconductor nanomembrane transfer printing techniques, we have demonstrated a range of ultra-compact high performacne photonic and electronic devices on silicon and on flexible substrates.By sandwiching InGaAsP quantum well cavity in between two single –layer silicon Fano resonance photonic crystal membrane reflectors (MR), membrane reflector vertical-cavity surface- emitting lasers (MR-VCSELs) were proposed and demonstrated. We will report our recent progresses on this new type of membrane lasers, which can be built on silicon, and on flexible substrates.Ultra-compact high quality factor optical filters have also been realized experimentally, based on Fano resonances in single or coupled bi-layer photonic crystal slabs, without or with lattice displacements. Theoretically, with the control of lattice displacement between two coupled photonic crystal slabs layers, optical filter Q factors can approach 211,000,000 or infinite. Experimentally optical filters with quality factors up to 80,000 have been demonstrated. Finally, we will review other type of Fano resonance based optical structures, such as vertical to in-plane couplers, and beam routing structures, for integrated silicon photonics. The convergence of nanomembranes and Fano resonance photonic crystals offer unprecedented opportunities for unique electronic and photonic devices for 3D multi-functional Si CMOS photonics, flexible, bio-inspired/integrated photonic/electronic systems, and multi-spectral multi-color infrared imaging and sensing systems, etc. The work was supported by US AFOSR, ARO and NSF.

Low Thermal Budget Au-Free Hf-Based Ohmic Contacts on InAlN/GaN Heterostructures

IntroductionThe InAlN/GaN heterostructures are attractive to researchers for high-power and high-speed applications owing to their unique properties such as high breakdown voltage, large bandgap, and strong polarization effects (thus leading to high 2DEG carrier density). Traditionally, InAlN/GaN high electron mobility transistors (HEMTs) are commonly fabricated with Ti/Al/Ni/Au ohmic contacts. However, Au is not compatible with Si process owing to its high diffusivity in Si. With the commercial availability of large GaN-on-Si wafers, Si CMOS compatible ohmic contacts for InAlN/GaN HEMTs are desirable, as this will allow their fabrication in incumbent Si foundaries, thus containing production costs. Furthermore, Ti/Al/Ni/Au contacts need a high annealing temperature (>800 oC) to achieve good ohimc properties on InAlN/GaN substrates [1-3], thus making it difficult to implement gate-first process, which is useful for the self-aligned process development. In this study, we report Au-free Hf/Al/Ta ohmic contacts on InAlN/GaN-on-Si with low contact resistance (Rc) and contact resistivity (ρc) achieved using a low annealing temperature (600 oC). The contact carrier transportation mechanism and preliminary thermal stability study are also investigated.ExperimentThe InAlN/GaN-on-Si wafer used in the experiment has a 9 nm Al0.82In0.18N barrier layer and 1 nm AlN spacer layer, grown on GaN buffer layer. Transfer Line Method (TLM) was used to evaluate the contact electrical properties. After mesa isolation formation by BCl3/Cl2 ICP etch, contact window patterning was carried out, followed by Hf/Al/Ta (15/200/20 nm) deposition by sputtering and metal lift-off to form contacts. Annealing of contacts was carried out in vacuum for 1 min at various temperatures (from 550 to 700 oC). SIMS and STEM were used to examine the interaction between Hf/Al/Ta and InAlN/GaN, and interface morphology, respectively. Rc, ρc and substrate sheet resistance (Rsh) were also measured as a function of temperature to analyze the contact carrier transportation mechanism. In addition, thermal aging test was conducted at 350 oC in air for more than 200 hours to assess the Hf/Al/Ta contact thermal stability.Results and DiscussionFigure 1 shows the variation of Rc and ρc of Hf/Al/Ta (15/200/20 nm) contacts on InAlN/GaN-on-Si with annealing temperature. The lowest Rc ~ 0.59 Ω.mm and ρc ~ 6.7×10-6 Ω.cm2 are attained after 600 oC annealing. SIMS results before and after 600 oC annealing indicate that nitrogen out diffusion from substrate could be critical to achieving good ohmic properties for Hf/Al/Ta on InAlN/GaN-on-Si. Fig. 2 shows the Rc, ρc and Rsh of Hf/Al/Ta (15/200/20 nm) contacts on InAlN/GaN-on-Si annealed at 600 oC as a function of measurement temperature. As shown, Rc has a marginal temperature dependence, as a result of ρc decreases, while Rsh increases with increasing temperature. The latter increase is due to optical phonon scattering. The temperature dependence of ρc indicates that electron thermionic field emission (TFE) may take place across Hf/Al/Ta contact on InAlN/GaN-on-Si. On the other hand, the high 2DEG carrier density of our InAlN/GaN-on-Si substrate (1.2×1013 cm-2) suggests that field emission (FE) may also happen. However, as FE is temperature independent, this transport component is unlikely to be dominant. The STEM image shown in Fig. 3 depicts the absence of spikes or contact inclusions in the thin InAlN barrier layer and its smooth interface with Hf/Al/Ta contact (likely as a result of the low annealing temperature at 600 oC). This reduces the tunneling mechanism. Hence, it is reasonable to conclude that electron TFE is the dominant transport mechanism between Hf/Al/Ta and InAlN/GaN. Finally, in the thermal aging test, no obvious change in Rc was observed after 200 hours at 350 oC in air ambient, indicating a thermal stable property for Hf/Al/Ta contacts.ConclusionIn summary, Hf/Al/Ta ohmic contacts on AlInN/GaN-on-Si have been realized with Rc ~ 0.59 Ω.mm and ρc ~ 6.7×10-6 Ω.cm2 after 600 oC annealing. SIMS results indicate that the ohmic contact formation could be due to nitrogen out diffusion from InAlN/GaN. Decrease of ρc with increasing temperature, coupled with the absence of spike formation or contact inclusions in the thin InAlN barrier layer and its smooth interface with Hf/Al/Ta contact, indicates that electron TFE could be the dominant transport mechanism for the Hf/Al/Ta ohmic contacts on InAlN/GaN. Finally, preliminary study has shown that Hf/Al/Ta contacts are stable at 350 oC in air.

(Invited) GaN HEMT Fabrication in a 200mm Si Foundry Environment: The Time Has Come

In 2013 Raytheon began to integrate deep submicron (≤0.25 µm gate) 200mm GaN on Si HEMT processes within a commercial CMOS Si Foundry environment. When fully realized, these processes will demonstrate multi GHz GaN on Si MMICs by leveraging a fully subtractively processed transistor coupled with multi level copper based back end of line (Cu BEOL) processes. This work provides a status update on the progress towards that goal.

Epitaxial Ge-crystal arrays for X-ray detection

Monolithic integration of an X-ray absorber layer on a Si CMOS chip might be a potentially attractive way to improve detector performance at acceptable costs. In practice this requires, however, the epitaxial growth of highly mismatched layers on a Si-substrate, both in terms of lattice parameters and thermal expansion coefficients. The generation of extended crystal defects, wafer bowing and layer cracking have so far made it impossible to put the simple concept into practice. Here we present a way in which the difficulties of fabricating very thick, defect-free epitaxial layers may be overcome. It consists of an array of densely packed, three-dimensional Ge-crystals on a patterned Si(001) substrate. The finite gap between neighboring micron-sized crystals prevents layer cracking and substrate bowing, while extended defects are driven to the crystal sidewalls. We show that the Ge-crystals are indeed defect-free, despite the lattice misfit of 4.2%. The electrical characteristics of individual Ge/Si heterojunction diodes are obtained from in-situ measurements inside a scanning electron microscope. The fabrication of monolithically integrated detectors is shown to be compatible with Si-CMOS processing.

Single Event Gate Rupture in SiC MOS Capacitors with Different Gate Oxide Thicknesses

The leakage currents through the gate oxide of MOS capacitors fabricated on n-type 4H-Silicon Carbide (SiC) was measured under accumulation bias conditions with heavy-ion irradiation. The Linear Energy Transfer (LET) dependence of the critical electric field (Ecr) at which dielectric breakdown occurred in these capacitors with two different oxide thicknesses was evaluated. The MOS capacitors with thin gate oxide showed higher Ecr values than those with thick gate oxide. The linear relationship between the reciprocal Ecr and LET was observed for both MOS capacitors. The slope of LET dependence of 1/Ecr for SiC MOS capacitors was smaller than that for Si, suggesting that SiC MOS devices are less susceptible to single-event gate rupture (SEGR) than Si MOS devices.

Room-temperature bonding of heterogeneous materials for near-infrared image sensor

A room-temperature bonding technique using cone-shaped microbumps with the aid of ultrasonic vibration is applied to the fabrication of a near-infrared (NIR) image sensor. The image sensor is fabricated using the chip-on-chip integration of an InGaAs photodiode array on an InP substrate and a Si CMOS readout IC. The pixel pitch is 25 µm to compose quarter-VGA class (320 × 256 pixels) resolution. A high-quality imaging of a heated object is demonstrated. Bonding of the VGA array with 15 µm pitch is attempted to realize a high-resolution image sensor.

Accurate Characterization of Interface State Density of SiC MOS Structures and the Impacts on Channel Mobility

We focused on the inability of the common high-low method to detect very fast interface states, and developed methods to evaluate such states (CψS method). We have investigated correlation between the interface state density (DIT) evaluated by the CψS method and MOSFET performance, and found that the DIT(CψS) was well reflected in MOSFET performance. Very fast interface states which are generated by nitridation restricted the improvement of subthreshold slope and field-effect mobility.

Accounting for variability in the design of circuits with organic thin-film transistors

We experimentally verify that the methodology to account for local parameter variations and transistor mismatch known in Si CMOS technologies can be transposed to organic thin-film transistor technologies, and we present a design case that makes use of design for variability. Transistor parameter variation decreases with the square root of the transistor footprint. As a consequence, Monte Carlo simulations which take this effect into account can be executed to better predict the final circuit yield. The design case in this work is an 8-bit, organic RFID transponder chip. The yield prediction by simulations corresponds to the finally observed circuit yield.

Microwave noise characterization of graphene field effect transistors

The microwave noise parameters of graphene field effect transistors (GFETs) fabricated using chemical vapor deposition graphene with 1 μm gate length in the 2 to 8 GHz range are reported. The obtained minimum noise temperature (Tmin) is 210 to 610 K for the extrinsic device and 100 to 500 K for the intrinsic GFET after de-embedding the parasitic noise contribution. The GFET noise properties are discussed in relation to FET noise models and the channel carrier transport. Comparison shows that GFETs can reach similar noise levels as contemporary Si CMOS technology provided a successful gate length scaling is performed.

Irradiation tests and expected performance of readout electronicsof the ATLAS Hadronic Endcap calorimeter for the HL-LHC

The readout electronics of the ATLAS Hadronic Endcap Calorimeterwill have to withstand an about 3–5 times higher radiation dosesat the future high-luminosity LHC compared to the LHC design values.The radiation damages of the front-end electronics made in GaAs technologycould significantly affect the hadronic endcap calorimeter performance. Recentmeasurements of characteristics of neutron and proton irradiated ASICs atroom and liquid argon temperatures are reported, which allow an improvedassessment of the expected degradation in high-luminosity LHC conditions.The results of these measurements are furthermore applied to simulations ofthe calorimeter performance. Results from replacement technologies, like Si CMOS,are also presented.

Performance and Variability Studies of InGaAs Gate-all-Around Nanowire MOSFETs

Furthering Si CMOS scaling requires development of high-mobility channel materials and advanced device structures to improve the electrostatic control. We demonstrate the fabrication of gate-all-around (GAA) indium gallium arsenide (InGaAs) MOSFETs with highly scaled atomic-layer-deposited gate dielectrics. InGaAs, with its high electron mobility, allows higher drive currents and other on-state performance compared to silicon. The GAA structure provides superior electrostatic control of the MOSFET channel with outstanding off-state performance. A subthreshold slope of 72 mV/dec, electron mobility of 764 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s, and an on-current of 1.59 mA/μm are demonstrated, for example. Variability studies on on-state and off-state performances caused by the number of nanowire channels are also presented.

Electrical and physical properties of 4H-SiC MOS interface with electron cyclotron resonance microwave nitrogen plasma post-oxidation annealing

An electron cyclotron resonance microwave nitrogen plasma post-oxidation annealing process was proposed to passivate the 4H-SiC MOS interface. The effects of this process on the electrical and physical properties of SiC MOS interface were investigated by current–voltage, capacitance–voltage, secondary ion mass spectrometry, and X-ray photoelectron spectroscopy measurements. By controlling the annealing period, this process could significantly reduce the density of interface traps (Dit) in the entire upper half of SiC band gap without degrading the oxide insulating properties. A 10-min annealing at 600°C produces the best result. The incorporated nitrogen, which is distributed throughout bulk SiO2 and SiO2/SiC interface, could reduce the content of SiOxCy and carbon clusters by forming some deep-level Si–N and C–N bonds. These results illustrate the physical modifications of SiC MOS interface induced by this process and explain the possible mechanism responsible for the observed reduction in Dit in different energy ranges.

(Invited) SiC MOS Interface States: Difference between Si Face and C Face

This paper discusses the differences between Si-face and C-face MOS interfaces in 4H-SiC MOSFETs. The two interfaces exhibit unique electrical characteristics, which will be linked with the differences in interface defects. We carried out an electrically detected magnetic resonance (EDMR) study on Si-face and C-face 4H-SiC MOSFETs, and found that there are different types and different amounts of interface defects on each interface. We discussed the EDMR results in comparison with the electrical characteristics of Si-face and C-face MOSFETs.

(Invited) Integration of High-κ Dielectrics on Epitaxial (100), (110) and (111) Germanium for Multifunctional Devices

With continued scaling of Si CMOS technology, new channel materials and device architectures are needed to address power consumption and constrained high-speed operation. With the demonstration of n-channel III-V transistors, the development of equivalent p-channel transistor is mandatory to realize energyefficient CMOS logic. The bulk transport properties of Ge make it an ideal candidate for p-channel transistor. The ultra-high hole mobility Ge can be realized through a III-V/Ge/III-V transistor configuration with different surface orientations would enable much faster switching, thus addressing dynamic power consumption, while the superior high- κ gate dielectric and larger bandgap barrier would help minimize OFF-state leakage. This paper discusses the i) in-situ growth of III-V/Ge/III-V heterostructure, ii) tailor-made surface orientations of Ge enable to achieve both high-hole and high-electron mobilities, and iii) band offsets of high- κ dielectrics on crystallographic oriented epitaxial (100)Ge, (110)Ge, and (111)Ge layers using solid state molecular beam epitaxy.

Impact of III–V and Ge Devices on Circuit Performance

III-V and germanium (Ge) field-effect transistors (FETs) have been studied as candidates for post Si CMOS. In this paper, the performance of various digital blocks and static random access memory (SRAM) with different combinations of Si, III-V and Ge devices are studied. SPICE-compatible III-V n-channel FET (nFET) and Ge p-channel FET (pFET) models are developed for the analysis. The delay and energy of the different combinations are estimated and compared. In typical digital design, the driving capability of the nFET and pFET should be matched for optimum noise margin and performance. The combination of III-V nFET with low input capacitance and Ge pFET achieves the best energy-delay performance for many digital logic circuits. The read margin of SRAM is maximized with a Si pass-gate, and an inverter of III-V nFET and Ge pFET.

A new type of glucose biosensor based on surface acoustic wave resonator using Mn-doped ZnO multilayer structure

This work reports a high-performance Mn-doped ZnO multilayer structure Love mode surface acoustic wave (SAW) biosensor for the detection of blood sugar. The biosensor was functionalized via immobilizing glucose oxidase onto a pH-sensitive polymer which was attached on Mn-doped ZnO biosensor. The fabricated SAW glucose biosensor is highly sensitive, accurate and fast with good anti-interference. The sensitivity of the SAW glucose biosensor is 7.184MHz/mM and the accuracy is 6.96×10−3mM, which is sensitive and accurate enough for glucose monitoring. A good degree of reversibility and stability of the glucose sensor is also demonstrated, which keeps a constant differential frequency shift up to 32 days. Concerning the time response to human serum, the glucose sensor shows a value of 4.6±0.4min when increasing glucose concentrations and 7.1±0.6min when decreasing, which is less than 10min and reach the fast response requirement for medical applications. The Mn-doped ZnO Love mode SAW biosensor can be fully integrated with CMOS Si chips and developed as a portable, passive and wireless real time detection system for blood sugar monitoring in human serum.

Radiation Effects in SiGe Technology

Silicon-Germanium (SiGe) technology effectively merges the desirable attributes of conventional silicon-based CMOS manufacturing (high integration levels, at high yield and low cost) with the extreme levels of transistor performance attainable in classical III-V heterojunction bipolar transistors (HBTs). SiGe technology joins together on-die high-speed bandgap-engineered SiGe HBTs with conventional Si CMOS to form SiGe BiCMOS technology, including all the requisite RF passive elements and multi-level thick-Al metalization required for high-speed circuit design. Such an silicon-based integrated circuit technology platform presents designers with an ideal division of labor for realizing optimal solutions to many performance-constrained mixed-signal (analog + digital + RF) systems. The unique bandgap-engineered features of SiGe HBTs enable several key merits with respect to operation across a wide variety of so-called “extreme environments”, potentially with little or no process modification, ultimately providing compelling advantages at the circuit and system level, across a wide class of envisioned commercial and defense applications. Here we give an overview of this interesting field, focusing primarily on the intersection of SiGe HBTs, and circuits built from them, with radiation-intense environments such as space.

Characterization of Si hybrid CMOS detectors for use in the soft X-ray band

We report on the characterization of four Teledyne Imaging Systems HAWAII Hybrid Si CMOS detectors designed for X-ray detection. Three H1RG detectors were studied along with a specially configured H2RG. Read noise measurements were performed, with the lowest result being 7.1e− RMS. Interpixel capacitive crosstalk (IPC) was measured for the three H1RGs and for the H2RG. The H1RGs had IPC upper limits of 4.0–5.5% (up & down pixels) and 8.7–9.7% (left & right pixels), indicating a clear asymmetry. Energy resolution is reported for two X-ray lines, 1.5 & 5.9keV, at multiple temperatures between 150 and 210K. The best resolution measured at 5.9keV was 250eV (4.2%) at 150K, with IPC contributing significantly to this measured energy distribution. The H2RG, with a unique configuration designed to decrease the capacitive coupling between ROIC pixels, had an IPC of 1.8±1.0% indicating a dramatic improvement in IPC with no measurable asymmetry. We also measured dark current as a function of temperature for each detector. For the detector with the lowest dark current, at 150K, we measured a dark current of 0.020±0.001 (e−s−1pixel−1). There is also a consistent break in the fit to the dark current data for each detector. Above 180K, all the data can be fit by the product of a power law in temperature and an exponential. Below 180K the dark current decreases more slowly; a shallow power law or constant must be added to each fit, indicating a different form of dark current is dominant in this temperature regime. Dark current figures of merit at 293K are estimated from the fit for each detector.

(Invited) Heterogeneous Integration of III-V Devices and Si CMOS on a Silicon Substrate

Standard Si CMOS and SiGe BiCMOS enable unparalleled integration density, yield, and functionality on a single chip. In addition to realization of high performance mixed signal circuits, such as data converters, there have been many impressive demonstrations of highly integrated RF chips, including full multi-element phased arrays at mm-wave frequencies. However, the performance is not ideal because silicon cannot compete with III-V technologies in terms of power density, efficiency, noise figure, dynamic range or linearity, and speed. Heterogeneously integrating III-V devices with the CMOS gives the designers state of art III-V performance combined with the integration density and functionality of silicon. We present the status of the direct growth/fabrication of InP HBT and GaN HEMT materials/devices on a silicon substrate containing high density Si CMOS. The integration process is similar to the SiGe BiCMOS process and can be considered a III-V BiCMOS process.