Si Channel Research Articles

Demonstration of Steep Switching Behavior Based on Band Modulation in WSe2 Feedback Field-Effect Transistor.

Feedback field-effect transistors (FBFETs) have been studied to obtain near-zero subthreshold swings at 300 K with a high on/off current ratio ~1010. However, their structural complexity, such as an epitaxy process after an etch process for a Si channel with a thickness of several nanometers, has limited broader research. We demonstrated a FBFET using in-plane WSe2 p-n homojunction. The WSe2 FBFET exhibited a minimum subthreshold swing of 153 mV/dec with 30 nm gate dielectric. Our modeling-based projection indicates that the swing of this device can be reduced to 14 mV/dec with 1 nm EOT. Also, the gain of the inverter using the WSe2 FBFET can be improved by up to 1.53 times compared to a silicon CMOS inverter, and power consumption can be reduced by up to 11.9%.

(Keynote) Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices

After a short description of the evolution of metal-oxide-semiconductor (MOS) device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material properties of complicated Si/SiGe multi-layer stacks used for complementary field effect transistor (CFET) devices. They contain two different Ge concentrations and have been grown using conventional process gases. A relatively high growth temperature is used to obtain acceptable Si and SiGe growth rates. Still island growth has been suppressed for Ge concentrations up to 40%. Excellent structural and optical material properties of the Si/SiGe multi-layer stack will be reported, with up to 3 + 3 Si channels in the top and bottom part of the stack, respectively. The absence/presence of lattice defects has been verified by room temperature photoluminescence measurements. Photoluminescence measurements at low temperatures are used to study band-to-band luminescence from individual sub-layers and to illustrate the optical material quality of the CFET stack.

Advanced SiGe:B Raised Sources and Drains for p-type FD-SOI MOSFETs

We have evaluated the feasability of selectively growing, with a chlorinated chemistry, 20 to 30 nm thick SiGe:B Raised Sources and Drains with Ge concentration gradients (from 50% down to 20%-30%, typically) on each side of FD-SOI transistors. The motivation was twofold: (i) inject meaningful amounts of compressive strain in the channel of p-type MOS devices thanks to high Ge concentrations in layers sitting in the same plane than Si or SiGe channels and (ii) benefit from lower Ge concentration SiGe layers on top that are easier to germano-silicide. Growing a thin Si(:B) cap on SiGe:B otherwise yields more uniform and stable contacts. We have thus studied the Si capping of SiGe 20% or 30% layers. As growth has to be conducted, for Si, at temperatures significantly higher than that of SiGe (750°C, to be compared with 700°C for SiGe 20% and 650°C for SiGe 30%, typically), we have quantified the impact of using temperature ramping-ups with SiH2Cl2 + HCl flowing into the growing chamber. The purpose of such active ramps was to prevent elastic strain relaxation, e.g. the formation of SiGe surface undulations that would happen with temperature ramps under H2 only.

High Performance CMOS RF Switch Based on Highly Carbon Doped Raised Source/Drain Regions

The demand for high-performance Radio Frequency (RF) CMOS RF SOI (Silicon on Insulator) switches has rapidly increased, driven by the need for advanced wireless technologies (1). In this paper we give new insights on high carbon incorporation, where a Si(1-y)Cy layer with 1% of substitutional carbon (y = Csub) is grown on 40 nm on top on silicon. This layer is used for Raised Source/Drain (RSD) to strain the Si channel, for reducing on-state resistivity (Ron) and which should result in a theoretical 16% gain in current (3), (4). Si(1-y)Cy growth parameters were carefully optimized to increase Csub. Firstly, with the reduction of the temperature. Then, with H2 carrier gas reduction and total pressure increase. These two process modifications have a positive impact on the carbon concentration, thanks to the higher growth rate, without layer relaxation (5).

Defect-Free SiGe/Si Multistacks for Next-Generation CFET Architectures

The advancement of CMOS technology nodes demands increasingly complex device architectures. In this frame, the epitaxial deposition of complicated SiGe/Si multistacks presents a significant technology challenge required to enable such cutting-edge devices. This work presents the characterization of defect-free multistacks featuring SiGe layers with two possible Ge concentrations and incorporating either two or six stacked Si nanosheets. Our comprehensive analysis reveals good matching with the nominal structures and demonstrates remarkable repeatability of the Si channels. Furthermore, the multistacks exhibit ideal surface morphology, crucial for subsequent processing steps. Notably, the study also highlights optimal wafer-to-wafer repeatability, a key factor in ensuring consistent performance across large-scale production.

Junction Piezotronic Transistor Arrays Based on Patterned ZnO Nanowires for High-Resolution Tactile and Photo Mapping.

Recently, a great deal of interest has been focused on developing sensors that can measure both pressure and light. However, traditional sensors are difficult to integrate into silicon (Si)-based integrated circuits. Therefore, it is particularly important to design a sensor that operates on a new principle. In this paper, junction piezotronic transistor (JPT) arrays based on zinc oxide (ZnO) nanowire are demonstrated. And the JPT arrays show high spatial resolution pressure and light mapping with 195 dpi. Because ZnO nanowires are arranged vertically above the p-type Si channel's center of the transistor, the width of the heterojunction depletion region is constricted by the positive piezoelectric potential generated by strained ZnO. In addition, photogenerated charge carriers can be created in the Si channel when JPT is stimulated by light, which increases its electrical conductivity. Consequently, the external pressure and light distribution information can be obtained from the variation in the output current of the device. The prepared JPT arrays can be compatible with Si transistors, which make them highly competitive and make it possible to incorporate both pressure and light sensors into large integrated circuits. This work will contribute to many applications, such as intelligent clothing, human-computer interaction, and electronic skin.

Sensitivity, linearity, and noise evaluation of L‐shaped dielectrically modulated label free tunnel field‐effect transistor biosensor

AbstractThis research article examines a L‐shaped dielectrically modulated label free TFET (L‐DM‐TFET) biosensor for the purpose of detecting different biomolecules using a label‐free biosensing detection technique. The proposed structure allows for the recognition of biomolecules by modulating various electrical properties, such as the drain current, transconductance, and linearity parameters. The source region of the proposed TFET incorporates a SiGe (source)/Si (channel) heterojunction, utilizing a low bandgap material of SiGe. This heterojunction is employed to enhance the ON‐state current of the devices. The materials used and the fabrication steps involved in our proposed device are compatible with complementary metal‐oxide‐semiconductor (CMOS) technology. This analysis is conducted using a calibrated Silvaco technology computer‐aided design (TCAD) simulator. Additionally, by considering a dielectric constant range of 1–12, we calculate various figure of merits (FOMs) parameters for the device. These include evaluation of linearity, sensitivity, and noise characteristics. Furthermore, we have conducted an analysis of linearity FOMs, such as VIP2, VIP3, IIP3, and IMD3 for the proposed device under study. Additionally, the linearity analysis of the presented tunneling FET (TFET) indicates the device's excellent performance in distortionless switching operations. Consequently, the L‐shaped dielectrically modulated biosensor holds potential suitability for high‐speed circuit designs.

Enlargement of Memory Window of Si Channel FeFET by Inserting Al₂O₃ Interlayer on Ferroelectric Hf₀.₅Zr₀.₅O₂

Enlargement of Memory Window of Si Channel FeFET by Inserting Al₂O₃ Interlayer on Ferroelectric Hf₀.₅Zr₀.₅O₂

Highly oriented crystalline si on epitaxial Gd2O3/Si(111) substrate using low-cost Radio Frequency sputtering for Silicon on Insulator application

Silicon-on-Insulator (SOI) technology has been the center of attraction with the advancement in Radio Frequency (RF) technology and the advent of Internet-of-Things due to its low-power operation with reduced parasitic and short-channel effects. However, the state-of-the-art smart-cut method used for the SOI wafer is costly. Alternatively, the notion of using the Si channel layer on epitaxial rare-earth oxide has been proposed. In literature, the existing techniques used to achieve the same, such as Molecular beam Epitaxy or reduced-pressure chemical vapor deposition technique, are either costly or non-high-volume manufacturable. In this context, we propose a method to fabricate the highly oriented crystalline Si(111) channel layer (Top-Si) on an epitaxial Gd2O3/Si(111) virtual substrate (SOXI) utilizing the solid phase epitaxy using the high-volume manufacturing friendly (HVM), low-cost RF magnetron sputtering technique. First, we have shown the multicrystalline Si and epitaxial Gd2O3 layer grown on Si(111) substrate, as confirmed using high-resolution X-ray diffraction (HRXRD) and Transmission Electron Microscopy (TEM). Second, we investigated the impact of rapid thermal annealing at 850 °C on the heterostructure using HRXRD and TEM. It is observed that the high-temperature annealing transforms the Top-Si layer into the highly oriented crystalline Si(111) layer by fusing smaller grains towards larger grains. Hence, we demonstrate a low-cost, HVM-friendly technique for the fabrication of SOXI wafers.

Nanowire FETs With Nearly Single-Crystalline Si Channels by NiSi2-Seed Initiated Lateral Epitaxial Crystallization (SILEC)

Nanowire FETs With Nearly Single-Crystalline Si Channels by NiSi₂-Seed Initiated Lateral Epitaxial Crystallization (SILEC)

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Nanosheet (NS) gate-all-around (GAA) devices have demonstrated advantages in device performance and area scaling over finFET devices [1-11]. Enablement and future scaling of GAA devices require robust etch processes for Inner Spacer (IS) and Channel Release (CR) for well-controlled device performance and yield (Fig. 1). CR requires an isotropic, complete etch of the sacrificial SiGe layer with extremely high selectivity to the spacer (Sp0), IS, and Si channels. Furthermore, during CR, the Si channels must be released simultaneously for all sheet widths (WNS) [1], which range from 20nm to 100nm, necessitating significant over-etch (OE) on the narrowest sheets. We demonstrated excellent device performance across all WNS with more than 150 % OE on the widest sheets [1]. However, this extreme OE makes the pFET source/drain (S/D) SiGe:B especially vulnerable to damage. In this paper, we explore several mechanisms that result in SiGe:B S/D damage and demonstrate how to prevent the damage with IS, CR, and S/D epitaxial optimization.The S/D Si:B and Si:P used in our high-performance test devices are not susceptible to damage during CR due to high etch selectivity [2]. Thus, SiGe:B S/D is required to evaluate the mechanisms causing S/D damage. To enable these studies, we developed high-quality S/D SiGe:B, which shows substantial device performance improvement over our baseline S/D Si:B, with 150% increase in peak mobility, 50% reduction in Vt, and 45% reduction in Ron (Fig. 2).The ability to target IS thickness allows tuning of device performance through Cov and Ron and is critical for future device scaling. In addition, the IS plays a critical role as a physical barrier to prevent S/D damage during CR [1,2]; reducing IS thickness below a critical value can result in S/D damage. The optimal IS thickness is determined by balancing maximum device performance for all WNS while maintaining S/D integrity during CR. This process window can be maximized by optimizing the CR etch process, and can be further increased by integrating an Si:B buffer in the S/D epitaxy. We have developed four CR processes with different chemistries and evaluated their process windows.We evaluated S/D damage for two CR processes versus IS thickness. We observed no S/D damage with Process A until 4nm IS thickness at 50% OE (Fig. 3a). Process C showed no damage at 4nm IS thickness, even up to 100% OE. The plan-view TEM in Fig. 3a shows that S/D damage occurs at the corners of the S/D region as well as at the center, indicating several mechanisms for S/D damage (see Fig. 4): CR etch gas permeation through the IS, exposed S/D through pinholes in the IS or at the IS edges due to rounded IS shape, and exposed S/D at the intersection of the Si/SiGe fins and gate.To isolate and characterize permeation of the CR etch gas through the IS, we deposited various thicknesses of IS on SiGe/Si multilayers (Fig. 5a), then exposed the structures to CR Process A. The SiGe layers showed no damage until the IS layer was thinned to <1nm. The difference in critical thickness for etch gas permeation on fully integrated structures compared to these test structures (4nm compared to <1nm) could be attributed to the other mechanisms.S/D damage due to IS permeation can be prevented by a better quality IS; by optimizing the CR chemistry to tune the selectivity between the sacrificial SiGe and the S/D SiGe:B (Fig. 5b); or by integrating a Si:B buffer prior to S/D SiGe:B deposition (Fig. 6). The process window then can be maximized by selecting the best CR process since selectivity to Si:B and permeation through the IS varies with the chemistry. Fig. 7 shows the improvement in the process window with a 2nm Si:B buffer on wafers with no IS for Processes A, B and C.The other S/D damage mechanisms highlighted in Fig. 4 are characterized in Fig. 3b. The S/D damage starts at the corners of the active region and the extent of damage increases with CR OE. These failure modes require changes in integration to improve the Sp0 at the fin-gate corner, reducing the IS rounding, or creating a straighter etch front across the sheet [2].S/D damage during CR is a significant issue in NS architecture. This can be mitigated by optimizing the CR etch process, incorporating an Si:B buffer layer, improving the IS quality or shape, and improved integration. Understanding these mechanisms is critical to ensure robust S/D quality with scaling for future technology nodes. Figure 1

The Structural Performance of a Novel Double‐Stacked Heterogeneous Gate Heterojunction Tunneling Field‐Effect Transistor

In this work, an original Si/SiGe heterojunction tunneling field‐effect transistor which has a double‐stacked heterogeneous oxide gate (HfO2/Al2O3) structure (DSG–HJ–TFET) is designed and investigated by Sentaurus technology computer aided design (TCAD) simulation software. To ensure good interface quality, a stacked oxide gate dielectric of Al2O3 and HfO2 is proposed. The on‐state current (Ion) is increased though improving the carrier mobility degradation caused by the poor quality of interface between the high‐κ dielectric and semiconductor. Moreover, a heterojunction with SiGe (source)/Si (channel) and pocket layer which is inserted between the source region and the channel is adopted to reduce the tunneling barrier and improve the Ion. Therefore, the higher Ion is obtained by the proposed DSG–HJ–TFET. In the simulation results, it is shown that Ion of DSG–HJ–TFET is increased by three orders of magnitude compared with that of the conventional high‐κ gate dielectric TFET structure. In addition, the off‐state current (Ioff) of 4.91 × 10−11 μA μm−1, the minimum subthreshold swing of 14 mV dec−1, the Ion/Ioff ratio of 1.13 × 1012, transconductance of 260 μS μm−1, fT of 49.8 GHz, and gain bandwidth product (GBW) of 7.2 GHz are obtained. The propose DSG–HJ–TFET is favored in ultralow‐power applications for the rather good performance.

Monolithic SOI through-wafer Knudsen pumps with mechanically robust Si channels

Knudsen pumps (KPs) generate gas flow using thermal transpiration in narrow channels with a longitudinal temperature gradient. With no moving parts, KPs offer long lifetime and are attractive for complex microfluidic systems. Although high performance was previously reported in microfabricated KPs that utilized suspended dielectric membranes to construct the pumping channels, this approach can limit the mechanical robustness and complicate the fabrication process. In this work, we present monolithically microfabricated KPs without using suspended membranes. These types of structures significantly improve the mechanical robustness, allow a wider process window, and simplify the microfabrication process. The pumping channels in this work are 14 µm in length, 1.2 × 200 µm2 in cross-section, vertically oriented, and with rigid silicon and dielectric sidewalls; the overall structures are easily manufacturable. This work primarily focuses on two core KP designs, which incorporate 4 and 6 parallel pumping channels in ≈ 11 and 17 mm2 footprints, respectively. The scaling capability is also investigated preliminarily in a design with 45 parallel pumping channels. The KPs were fabricated on a silicon-on-insulator wafer by a six-mask lithographic process with standard fabrication steps. This process eliminated the use of complicated trench refill, polish, and sacrificial dry etch steps that were required for the previously reported KPs with suspended membranes. At atmospheric pressure, the 4-channel KPs provided a blocking pressure of 620 Pa and maximum flow rate of 0.041 sccm through 0.001 mm2 channel area, using 2 W applied power. This maximum flow rate per unit channel area (sccm/mm2) is superior to that of the KPs with suspended membranes. For all the KP designs, the experimentally measured pumping performance well matched the modeling results, with <15 % discrepancy. The fabrication simplicity and reliability of the mechanically robust KPs can enable monolithic integration onto complex lab-on-a-chip systems.

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Nanosheet gate-all-around devices have demonstrated several advantages in device performance and area scaling over finFET devices with higher device density and improved electrostatic control. Robust inner spacer (IS) and channel formation is critical for high performance, reduced variability and good yield. An isotropic dry etch of the sacrificial SiGe layer with extremely high selectivity to gate spacer, IS and Si channels is necessary for high-quality channel formation over a wide range of sheet widths. Furthermore, the nFET Si:P and pFET SiGe:B source-drain (S/D) epitaxy must be isolated using inner spacers or buffers to prevent damage during Channel Release (CR). The damage can be further mitigated with optimized CR etch chemistry, enabling IS scaling. We highlight S/D damage mechanisms during CR, then demonstrate reduced S/D damage by co-optimization of the IS, CR chemistry and S/D epitaxy.

Extremely high selective Si1−xGex-film wet etchant generating highly dissolved oxygen via peracetic acid oxidant for lateral gate-all-around FETs with a logic node of less than 3-nm

For lateral gate-all-around (LGAA) field-effect transistors (FETs) having design rules of logic devices below 3-nm and 3D-DRAM below 10-nm, multi-stacked Si1−xGex/Si-films should be epitaxially grown on the Si surfaces, and a highly selective wet etching of Si1−xGex-film is essentially followed for forming nanoscale-thick (5–7 nm) Si channel multi-sheets. A high selective etchant has required a lateral Si1−xGex etch rate of >30 nm⋅min-1 and etch rate selectivity between Si1−xGex- and Si-films of >200:1 at patterned multi-stacked Si1−xGex/Si-films. The selective Si1−xGex-film etchant using an etching agent (HF), a selectivity enhancing agent (CH3COOH), and a strong oxidant peracetic acid (PAA; CH3COOOH) unlike a conventional oxidant (H2O2 or HNO3) presented an extremely high Si0.5Ge0.5-film etch rate (82 nm⋅min-1@5 wt% of PAA) and etch rate selectivity between the Si0.5Ge0.5- and Si-films (265:1). Thus, it performed sufficient lateral Si1−xGex-film etching in the 3 multi-stacked Si0.5Ge0.5/Si-films line pattern and satisfied the requirement for a selective etching of Si1−xGex-film for LGAA having a logic-node of less than 2.1-nm. The excellent Si1−xGex-film etch rate using PAA was driven by a lower decomposition energy, lower Gibbs free energy, and higher standard reduction potential compared to the oxidant H2O2. Therefore, the amount of diffused dissolved oxygen using 5 wt% PAA was ∼1.48 times higher than that of H2O2; hence, the chemical oxidation degree (GeOx, and SiOx-bonds on the Si0.5Ge0.5-film surface) for 5 wt% PAA was ∼1.1 times higher than that of H2O2. Furthermore, the etch rate of the Si0.5Ge0.5-film using 5 wt% PAA was ∼5.4 times higher than that of H2O2; thus, we provide a cost effective Si1−xGex-film etching process for LGAA.

Novel process integration flow of germanium-on-silicon FinFETs for low-power technologies

Germanium channel FinFET transistors process integration on a silicon substrate is a promising candidate to extend the complementary metal–oxide–semiconductor semiconductor roadmap. This process has utilized the legacy of state-of-art silicon fabrication process technology and can be an immediate solution to integrate beyond Si channel materials over standard Si wafers. The fabrication of such devices involves several complicated technological steps, such as strain-free epi layers over the Si substrate to limit the substrate leakage and patterning of narrow and sharp fins over germanium (Ge). To overcome these issues, the active p-type germanium layers were grown over n-type germanium and virtual substrates. The poly ((4-(methacryloyloxy) phenyl) dimethyl sulfoniumtriflate) was utilized as a polymeric negative tone e-beam resist for sub-20 nm critical dimensions with low line edge roughness, line width roughness, and high etch resistance to pattern p-Ge fins to meet these concerns. Here, the devices use the mesa architecture that will allow low bandgap materials only at the active regions and raised fins to reduce the active area interaction with the substrate to suppress leakage currents. This paper discusses the simple five-layer process flow to fabricate FinFET devices with critical optimizations like resist prerequisite optimization conditions before exposure, alignment of various layers by electron beam alignment, pattern transfer optimizations using reactive ion etching, and bilayer resist for desired lift-off. The Ge-on-Si FinFET devices are fabricated with a width and gate length of 15/90 nm, respectively. The devices exhibit the improved ION/IOFF in order of ∼105, transconductance Gm ∼86 μS/μm, and subthreshold slope close to ∼90 mV/dec.

An Analytical Approach to Study the Impact of Traps on Ge-Source Double Gate PNPN TFET

The analytical models for surface potential, electric field, and drain current of a Ge-source double gate hetero-structure PNPN Tunnel FET are developed taking into account the oxide-semiconductor interfacial trap charges. Although other researchers have used similar modeling techniques on various structures, the proposed structure has not yet utilized them when considering the source/drain depletion region and interfacial trap charges that reflect changes in the flat band voltage. The proposed device consists of Ge-source, Si1−xGex pocket (mole fraction 0.3), and Si channel and drain. Moreover, the non-uniform concentration of trap charges is considered at the oxide/semiconductor interfaces: 1013 cm−2 at HfO2/ Si1−xGex interface and 1012 cm−2 at HfO2/Si interface. 2D Poisson’s equation is solved with the help of parabolic potential approximation and different boundary conditions to develop the surface potential model. The developed potential model is subsequently used to construct the electric field model. The drain current model of the proposed TFET is finally developed with the help of the generated electric field and some other parameters. All the developed models are validated using TCAD-simulated data. The studies show that there is good agreement between the simulated and modeled results, ensuring the applicability of the device in charge-trapped memory systems based on tunneling.

Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness

Compressively strained SiGe is an interesting channel material for sub 45 nm p-MOSFETs because of its superior hole mobility (up to 10x over bulk Si channels) and compatibility with current Si manufacturing technologies. In this work, the impact of heterostructure composition and SiGe channel thickness on the electrical characteristics of p-MOSFET are studied. Using strained Si0.8Ge0.2 p-MOSFET, the thickness was altered to a few thicknesses of 3 nm, 5 nm, 7 nm, and 9 nm respectively. The optimal thickness was then used for Ge compositions (x = 0.2). The project was realized utilizing computer-aided Silvaco TCAD tools, with ATHENA tools creating the p-MOSFET structure and ATLAS tools doing the device simulation. The strained-Si1-xGex p-MOSFET and the Si p-MOSFET were compared in terms of their performances. The ID-VG and ID-VD characteristics, as well as the threshold voltage, VTH extraction, were the focus of the device simulation. The 7 nm thickness strained-Si0.8Ge0.2 p-MOSFET exhibited lower VTH than other SiGe thicknesses and the Si p-MOSFET which is VTH = 0.074 V. The lower threshold voltage of the strained-Si0.8Ge0.2 with 7 nm thickness indicating that the strained-Si1-xGex contributed to the decreased power consumption. In addition, the extracted IDsat for the strained-Si0.8Ge0.2 p-MOSFET with 7nm thickness provided higher IDsat compared to conventional Si p-MOSFET and other SiGe thicknesses devices. As compared to Si p-MOSFETs, the output characteristics of the strained-Si1-xGex demonstrated a drain current improvement by a factor of 1.01.

A Novel Low On−State Resistance Si/4H−SiC Heterojunction VDMOS with Electron Tunneling Layer Based on a Discussion of the Hetero−Transfer Mechanism

In this study, we propose a novel silicon (Si)/silicon carbide (4H−SiC) heterojunction vertical double−diffused MOSFET with an electron tunneling layer (ETL) (HT−VDMOS), which improves the specific on−state resistance (RON), and examine the hetero−transfer mechanism by simulation. In this structure, the high channel mobility and high breakdown voltage (BV) are obtained simultaneously with the Si channel and the SiC drift region. The heavy doping ETL on the 4H−SiC side of the heterointerface leads to a low heterointerface resistance (RH), while the RH in H−VDMOS is extremely high due to the high heterointerface barrier. The higher carrier concentration of the 4H−SiC surface can significantly reduce the width of the heterointerface barrier, which is demonstrated by the comparison of the conductor energy bands of the proposed HT−VDMOS and the general Si/SiC heterojunction VDMOS (H−VDMOS), and the electron tunneling effect is significantly enhanced, leading to a higher tunneling current. As a result, a significantly improved trade−off between RON and BV is achieved. With similar BV values (approximately 1525V), the RON of the HT−VDMOS is 88% and 65.75% lower than that of H−VDMOS and the conventional SiC VDMOS, respectively.

Novel SiGe/Si Heterojunction Double-Gate Tunneling FETs with a Heterogate Dielectric for High Performance.

In this paper, a new SiGe/Si heterojunction double-gate heterogate dielectric tunneling field-effect transistor with an auxiliary tunneling barrier layer (HJ-HD-P-DGTFET) is proposed and investigated using TCAD tools. SiGe material has a smaller band gap than Si, so a heterojunction with SiGe(source)/Si(channel) can result in a smaller tunneling distance, which is very helpful in boosting the tunneling rate. The gate dielectric near the drain region consists of low-k SiO2 to weaken the gate control of the channel-drain tunneling junction and reduce the ambipolar current (Iamb). In contrast, the gate dielectric near the source region consists of high-k HfO2 to increase the on-state current (Ion) through the method of gate control. To further increase Ion, an n+-doped auxiliary tunneling barrier layer (pocket)is used to reduce the tunneling distance. Therefore, the proposed HJ-HD-P-DGTFET can obtain a higher on-state current and suppressed ambipolar effect. The simulation results show that a large Ion of 7.79 × 10-5 A/μm, a suppressed Ioff of 8.16 × 10-18 A/μm, minimum subthreshold swing (SSmin) of 19 mV/dec, a cutoff frequency (fT) of 19.95 GHz, and gain bandwidth product (GBW) of 2.07 GHz can be achieved. The data indicate that HJ-HD-P-DGTFET is a promising device for low-power-consumption radio frequency applications.