Advanced SiGe:B Raised Sources and Drains for p-type FD-SOI MOSFETs

Abstract

We have evaluated the feasability of selectively growing, with a chlorinated chemistry, 20 to 30 nm thick SiGe:B Raised Sources and Drains with Ge concentration gradients (from 50% down to 20%-30%, typically) on each side of FD-SOI transistors. The motivation was twofold: (i) inject meaningful amounts of compressive strain in the channel of p-type MOS devices thanks to high Ge concentrations in layers sitting in the same plane than Si or SiGe channels and (ii) benefit from lower Ge concentration SiGe layers on top that are easier to germano-silicide. Growing a thin Si(:B) cap on SiGe:B otherwise yields more uniform and stable contacts. We have thus studied the Si capping of SiGe 20% or 30% layers. As growth has to be conducted, for Si, at temperatures significantly higher than that of SiGe (750°C, to be compared with 700°C for SiGe 20% and 650°C for SiGe 30%, typically), we have quantified the impact of using temperature ramping-ups with SiH2Cl2 + HCl flowing into the growing chamber. The purpose of such active ramps was to prevent elastic strain relaxation, e.g. the formation of SiGe surface undulations that would happen with temperature ramps under H2 only.