Short-channel Threshold Voltage Research Articles

Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance

ABSTRACTThe present boon in the research field of nanoscale device physics is attributed to a large extent by the development of non-conventional multiple gate MOS devices due to increased device packing density and enhanced gate electrostatic control over the channel. In this work, we have investigated the attributes of an asymmetric Double Gate metal oxide semiconductor field effect transistor (MOSFET) incorporating the novel theory of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate in a fully depleted Double Gate MOSFET. A two-dimensional analytical modeling of this Linearly Graded Asymmetric Double Gate MOSFET structure has been done to formulate a simplified expression for short channel threshold voltage, and an overall performance analysis of our proposed device has been presented to establish the superiority of our proposed structure in terms of superior short channel effect mitigation and a significant reduction in threshold voltage. The results obtained from our analytical analysis are found to be in good agreement with the simulation results, thereby, establishing the accuracy of our model.

Threshold voltage modeling and performance comparison of a novel linearly graded binary metal alloy gate junctionless double gate metal oxide semiconductor field effect transistor

Keeping pace with the current research trend dominated by development of junctionless devices, in this work, we have incorporated the innovative concept of work function engineering by continuous horizontal variation of mole fraction in a binary metal alloy gate into a junctionless double gate metal oxide semiconductor field effect transistor. We have thereby presented a new structure, a junctionless work function engineered gate double gate metal oxide semiconductor field effect transistor. A detailed analytical modeling of this novel transistor structure has been done based on the solution of two dimensional Poisson’s equation presenting a simplified expression for short channel threshold voltage. Based on analytical calculations, an overall performance comparison of junctionless work function engineered gate double gate and normal junctionless double gate metal oxide semiconductor field effect transistor has been investigated to establish the superiority of our proposed structure over its normal junctionless double gate counterpart in terms of reduced short channel effects, threshold voltage roll-off and drain induced barrier lowering.

Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is related to the short-channel threshold voltage roll-off and minimum channel length with and without a substrate bias. The benefit of a reverse substrate bias is investigated and understood in terms of the field and distribution of inversion charge in the silicon film. In particular, how a bulk-like short-channel effect is achieved when an accumulation layer is formed at the back surface. Furthermore, the effect of a high-κ gate insulator is studied and scaling implications discussed.

An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

In this paper, an analytical short-channel threshold voltage model is presented for a dual-metal-gate (DMG) fully depleted recessed source/drain (Re-S/D) SOI MOSFET. For the first time, the advantages of recessed source/drain (Re-S/D) and of dual-metal-gate structure are incorporated simultaneously in a fully depleted SOI MOSFET. The analytical surface potential model at Si-channel/SiO2 interface and Si-channel/buried-oxide (BOX) interface have been developed by solving the 2-D Poisson’s equation in the channel region with appropriate boundary conditions assuming parabolic potential profile in the transverse direction of the channel. Thereupon, a threshold voltage model is derived from the minimum surface potential in the channel. The developed model is analyzed extensively for a variety of device parameters like the oxide and silicon channel thicknesses, thickness of source/drain extension in the BOX, control and screen gate length ratio. The validity of the present 2D analytical model is verified with ATLAS™, a 2D device simulator from SILVACO Inc.

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the "virtual cathode" concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed Si1?x Ge x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.

A Novel Short-Channel Model for Threshold Voltage of Trigate MOSFETs With Localized Trapped Charges

Based on the scaling equation and perimeter-weighted-sum approach, a novel short-channel threshold voltage model for the trigate (TG) MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flatband voltage. The model shows how the positive/negative trapped charges, silicon thickness, silicon width, oxide thickness, and normalized damaged zone affect the threshold voltage behavior. The model is verified by the 3-D device simulator “DESSIS” and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced TG charge-trapped memory device.

Layout Scaling of $\hbox{Si}_{1-x}\hbox{Ge}_{x} \hbox{-Channel}$ pFETs

Through a combination of electrical measurements, technology computer-aided design simulations, and wafer bending experiments, the effect of elastic stress relaxation on the layout dependence of Si1-xGex-channel p-channel field-effect transistors (pFETs) is studied. This work focuses on scaling of the transistor width W, the active-area length (length of diffusion, LOD) for isolated transistors, and poly-to-poly length LP/P of nested configurations. A strong narrow-width current enhancement is reported, even for relatively large widths, above 100 nm. On the other hand, the layout dependence on LOD or LP/P is also predicted but only for aggressively scaled layouts (LOD or LP/P below 100 nm). W and LP/P scaling lead to current enhancement, whereas LOD scaling is expected to degrade performance. No significant dependence of short-channel threshold voltage on W, LOD, or LP/P was observed. This study indicates that, as higher germanium concentrations of the channel lead to more layout dependence, this concentration may need to be optimized carefully to combine high channel mobility with limited added design complexity. Moreover, the channel thickness should be kept as thin as possible, as layout dependence is enhanced for thicker channels.

Effect of Dynamic Bias Stress (AC) In Short-Channel (L=1.5μm) p-Type polycrystalline Silicon (poly-Si) Thin Film Transistors (TFTs) on the glass substrate

ABSTRACTWe have investigated the stability of short channel (1.5μm) p-Type polycrystalline silicon (poly-Si) Thin Film Transistors (TFTs) on the glass substrate under AC bias stress. The variation of threshold voltage in short channel poly-Si TFT was considerably higher than that of long channel poly-Si TFT. Threshold voltage of the short channel TFT was considerably moved to the positive direction during AC bias stress, whereas the threshold voltage of a long channel was rarely moved. The variation of threshold voltage in the short channel p-type TFT under AC bias stess was more compared to that under DC bias stress. The threshold voltage of short channel (L=1.5μm) poly-Si TFT was increased about -7.44V from -0.305V to -7.745V when VGS = 5 (base value) ~ -15V (peak value), VDS = -15V was applied for 3,000 seconds. This positive shift of threshold voltage and significantly degraded s-swing value in the short channel TFT under dynamic stress (AC) may be due to the increase of the stress-induced trap state density at gate insulator / channel interface region.

A 2D analytical model for SCEs in MOSFETs with high-k gate dielectric

In this paper, a two-dimensional (2D) analytical potential model for MOSFETs with high-k gate dielectric is derived based on solving a boundary value problem with 2D Poisson's equation. A novel approach to estimate short-channel threshold voltage (VT) roll-off analytically is also presented and an explicit expression for the short-channel VT roll-off is obtained. Results show that the minimum surface potential along the channel, the inverse slope of subthreshold current, short-channel VT roll-off and drain-induced barrier lowering (DIBL) predicted by the analytical model are in close agreement with 2D numerical simulation (TCAD Sentaurus) without any fitting parameters even down to a sub-20 nm channel length. This model offers a physical insight into short-channel effects and how each of the parameters of a MOSFET quantitatively impacts on ΔVT and other key features of the device. It also serves for compact modeling of high-k gate dielectric MOSFETs.

Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

AbstractFor the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

Characterization of High-Performance Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Circuits

Polycrystalline silicon (poly-Si) complementary metal–oxide–semiconductor (CMOS) circuits have been fabricated by using an advanced excimer-laser annealing method and a plasma-oxidation method. The 1-µm-long thin-film transistors (TFTs) were fabricated on arrays of laterally grown long and narrow grains, so that the majority of carriers were free from scattering at grain boundaries during propagation through the channel. The propagation delay time measured by a 21-stage ring oscillator was 175 ps and a power-delay product of 9×10-13 J/gate was obtained at a supply voltage of 3.3 V. The obtained propagation delay time was almost the same as those of bulk Si devices having the same gate length. Furthermore, we expect that 1-µm-long CMOS TFT circuits on glass will have a performance superior to that of 1-µm-long bulk Si devices when the short channel effect and threshold voltage fluctuation are controlled well.

Compact model of the quantum short-channel threshold voltage in symmetric Double-Gate MOSFET

A compact model for the threshold voltage in Double-Gate (DG) MOSFET is developed. The model takes into account short-channel effects, carrier quantization and temperature dependence of the threshold voltage. We assume a parabolic variation of the potential with the vertical position in the silicon film at threshold. An analytical expression for the surface potential dependence as a function of bias and position in the silicon film is also developed and used for the inversion charge calculation. The model has been fully validated by 2D quantum numerical simulation and is used to predict the threshold voltage roll-off in DG MOSFET with very short channel lengths and thin films. The comparison with measured threshold voltages shows that the model reproduces with an excellent accuracy the experimental data.

2-D modeling of potential distribution and threshold voltage of short channel fully depleted dual material gate SOI MESFET

A two-dimensional analytical model for the potential distribution along the bottom channel of the fully depleted region of dual material gate (DMG) SOI MESFET is presented. The potential distribution is modeled by solving the Poisson equation with proper boundary conditions. The model for the potential distribution is extended to derive an analytical expression for the threshold voltage. The accuracy of the model is verified by comparing the analytical results with the results of GENESISe device simulator for different device parameters. The comparison demonstrates an excellent agreement between the analytical and simulation results. The results reveal that the DMG structure introduces a step function in the bottom potential profile in the depleted region. This function reduces the drain induced barrier lowering (DIBL) effect when compared to the conventional single metal gate (SMG) structure. Finally, the effects of different DMG structure parameters on the amount of DIBL reduction are also investigated.

An Analytical Model of Short-Channel Effect for Metal–Oxide–Semiconductor Field-Effect Transistor with Insulated Shallow Extension

In this paper, we present an analytical short-channel threshold voltage model without any fitting parameter for the metal–oxide–semiconductor field-effect Transistor (MOSFET) with insulated shallow extension (ISE). Excellent agreements between the numerical simulated results and this model are obtained. Very good suppression of the short-channel effect is observed for this ISE MOSFET. Both the sidewall-oxide thickness and shallow-extension depth play a major role in containing the short-channel effect. The threshold-voltage equation is found by using the effective-doping model. The effective doping is derived from the knowledge of the channel potential. The channel potential is obtained by the scale-length approach to solve 2D Poisson's equation.

Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs

A physical, compact, short-channel threshold voltage model for undoped double-gate MOSFETs has been extended through a phenomenological approach to include the fringe-induced barrier lowering (FIBL) effect associated with high-permittivity (high- k) gate dielectrics. The resulting analytical model closely describes published numerical simulations over a wide range of device/material parameters. Exploiting the new device model, a concerted analysis combining FIBL-enhanced short-channel effects and gate direct tunneling current is performed on candidate high- k gate dielectrics to assess their overall impact on DG MOSFET scaling. It is projected that high- k gate dielectrics may extend DG MOSFET scaling beyond that with SiO 2 by 10–20% for a 2–3× smaller equivalent oxide thickness of high- k dielectrics than that of SiO 2.

A 2-D Analytical Solution for SCEs in DG MOSFETs

A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.

A two-dimensional analytical subthreshold behavior model for short-channel AlGaAs/GaAs HFETs

Based on the minimum heteroface potential through an evanescent-mode analysis of two-dimensional potential distribution, the comprehensive and accurate expressions for the short-channel threshold voltage and subthreshold swing for self-aligned gated AlGaAs/GaAs HFETs are developed. It is found that the 2-D electron gas is strongly affected by the DIBL effect which will significantly influence the subthreshold behavior of the AlGaAs/GaAs HFETs. Besides the doping density, the thickness of the spacer and doped body can aggressively affect the short-channel subthreshold behavior comprising threshold voltage shift and subthreshold swing degradation. This model not only gives physical insights into the short-channel effects in HFETs but also offers basic designing guideline for the small-geometry AlGaAs/GaAs HFETs.

A new simplified analytical short-channel threshold voltage model for InAlAs/InGaAs heterostructure InP based pulsed doped HEMT

A new analytical threshold voltage model for InAlAs/InGaAs heterostructure, InP based HEMT has been developed considering the short-channel effect in subthreshold regime. The model is developed following the MESFET analysis, considering fully depleted InAlAs region as two isolated depletions––one due to metal–semiconductor contact and other due to transfer of carriers from InAlAs region to the 2DEG quantum well. Poisson’s equation is solved using Green’s Function technique and the solution is then verified by comparing it with Numerical technique. The 2D threshold voltage obtained from our analysis was found to be in good agreement with 1D threshold voltage for higher gate lengths, thus proving the validity of our model.

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.

An accurate two-dimensional CAD-oriented model of retrograde doped MOSFETs for improved short channel performance

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter ( R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer ( d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.