Short-channel Metal Oxide Semiconductor Research Articles

Simulation study of a novel AlGaN/GaN L‐FER with ultralow turn‐on voltage and low reverse leakage

In this work, a novel AlGaN/GaN lateral field-effect rectifier (L-FER) with ultralow turn-on voltage (VT) and low reverse leakage current (IR) is proposed and verified by technology computer aided design (TCAD) Sentaurus. Through shortly contacting the short-channel metal–oxide–semiconductor (MOS) structure with an Ohmic-contact structure as the anode of the proposed L-FER, an ultralow VT can be realized. And by inserting a floating clamp (FC) electrode near the cathode-side MOS edge, the transverse channel potential at the MOS edge could be clamped to a small value. Thus, the high IR induced by the short-channel effect in the MOS structure could be suppressed. In contrast to the conventional short-channel L-FER, the proposed FC-L-FER exhibits about four orders of magnitude reduction in IR, without obvious degeneration in the forward current and VT. Moreover, the proposed FC-L-FER also delivers excellent reverse recovery characteristics.

On the Explicit Saturation Drain Current in the Generalized EKV Compact MOSFET Model

We present and discuss explicit closed-form expressions for the saturation drain current of short-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz–Krummenacher–Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert ${W}$ function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-current ratio, can be readily expressed as explicit functions of the terminal voltages.

Current-to-transconductance ratio technique for simultaneous extraction of threshold voltage and parasitic resistances in MOSFETs

In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage (VT) and parasitic source (RS) and drain (RD) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of RS, RD, and VT in any single MOSFET with the channel length modulation (CLM) and the structural asymmetry. The proposed method is experimentally verified through Si MOSFETs with intentional asymmetry by connecting an external resistor (Rext) to the source terminal. We experimentally confirmed that extracted RS, RD, and VT are independent of the drain bias (VDS) and intentional Rext employed for the asymmetry. We also compared the results with previously reported techniques.

Systematic circuit design and analysis using generalised g m / I D functions of MOS devices

The conventional approach to implementing analogue integrated circuits in nano-scale complementary metal oxide semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries. Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide semiconductor field effect transistors such that maximum efficiency is achieved for minimum power consumption and silicon area. Analytical-based design procedures can assist the designer in confronting the sizing challenge of the metal oxide semiconductor (MOS) devices. The procedures are, however, dependent on circuit topology, model parameters, and device physics. This study aims at presenting a systematic approach for analysis and design of analogue circuits in scaled CMOS. For this purpose, the behaviour of short-channel MOS devices is characterised in various process and temperature corners using an updated matrix representation of different device scales, bias conditions, and small-signal parameters. The details to effectively extract the matrix derivation of the technology model files are presented, enabling to devise generalised functions for the design and analysis of the circuits. The design examples include a 0.39 V – 28 µA reference circuit, and a 7.50 µA/V operational-transconductance amplifier with 1.0 V voltage supply in 90-nm CMOS.

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO2

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO₂

Physical origin of gate voltage‐dependent drain–source capacitance in short‐channel MOSFETs

For the first time, it is revealed that the physical origin of the gate–source voltage (V gs)-dependent drain–source capacitance in short-channel metal–oxide semiconductor field-effect transistors (MOSFETs) comes from the depletion capacitance components between the drain and channel end in the saturation region. On the basis of this origin, it is newly found that the V gs-dependent channel resistance should be connected in series with the drain–source capacitance to model the high-frequency (HF) response of the intrinsic output capacitance. The accuracy of an improved MOSFET model, including the channel resistance, is validated by observing the excellent agreement with the measured S-parameters in the wide range of V gs up to 40 GHz.

High-performance poly-Ge short-channel metal–oxide–semiconductor field-effect transistors formed on SiO2 layer by flash lamp annealing

To realize a stackable complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) on interlayer dielectrics for three-dimensional (3D) large-scale-integration devices, we investigated poly-Ge thin films formed by flash lamp annealing. The process resulted in crystalline grains of micrometer-order size, and the Hall-effect mobility of holes was as high as 200 cm2 V−1 s−1. A depletion-type trigate poly-Ge channel pMOSFET with a gate length of 80 nm formed on a poly-Ge film exhibited a drive current of 280 µA/µm at a drain voltage of −1 V and a gate overdrive of −1 V. The operation of inversion-type short-channel trigate poly-Ge nMOSFETs was also demonstrated.

Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC

In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal–mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

Modelling of Hot-Electron Energy in Short-Channel MOSFETs by Electrical Method

Channel hot-electron (HE) energy in short-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) is estimated based on electrical characterization. The HE assisted gate leakage is monitored, and its energy dependent tunnelling probability is calculated, from which the excess energy of HE is estimated. The credibility of the proposed method is supported by the experimental and theoretical results, and its accuracy in ultra-small-feature-size device application is also discussed.

Effect of Three Normal Mechanical Stresses on Electrical Characteristics of Short-Channel Metal–Oxide–Semiconductor Field Effect Transistor

The change in electrical characteristics due to mechanical stress is studied for short-channel metal–oxide–semiconductor field effect transistors (MOSFETs) fabricated on (001) substrate in advanced 65 nm technology. An experimental trial is carried out to investigate the effect of three independent components of mechanical stresses orthogonal to one another on drain current and threshold voltage using a pin-pressing apparatus and the cantilever method. The change in drain current agrees with the signs and magnitudes shown in the literature for surface stress on the (001) plane. On the other hand, the change versus stress vertical to the plane shows a peculiar phenomenon for pMOSFET. That is, the change decreases with the expected rate up to 90 MPa, but increases rapidly above 450 MPa. Although the physical mechanism is unclear at present, simultaneously generated biaxial horizontal strains possibly cause this peculiar phenomenon.

Effective channel length measurement of metal-oxide-semiconductor transistors with pocket implant using the subthreshold current-voltage characteristics based on remote Coulomb scattering

For deep submicron metal-oxide-semiconductor (MOS) transistors with pocket implant, the electron mobility of the short channel transistor is always smaller than that of the long channel transistor in the above-threshold regime, resulting in serious error in effective channel length (Leff) measurement based on the assumption that the mobility is independent of gate length. Our theory predicts that when the gate oxide is very thin the electron mobility is approximately equal for short and long channel MOS transistors in the subthreshold regime. Thus it is possible to perform Leff measurement in the subthreshold region of MOS transistors with ultrathin gate oxide.

Optimization of breakdown behaviour and short channel effects in MBE-grown vertical MOS-devices with local channel doping

In this paper we present an approach to enhance the breakdown characteristics in vertical short channel metal-oxide semiconductor (MOS) devices. A problem of vertical devices with channel length down to 100 nm is the breakdown, which already takes place at very low source-drain voltages. To overcome this problem we have designed a device with an intrinsic silicon region, which shows a significant enhancement of breakdown behaviour. Our devices show a breakdown voltage up to 14 V together with distinct reduction of short channel effects. A further benefit of using the vertical concept is the employment of local channel doping, leading to lower power dissipation in the MOS-device.

Miniaturization of an electron device using inverse problem methodology

The miniaturization of electron devices has its advantages in dense circuits and high frequency devices. As can be seen in the current literature, considerable effort is devoted on the problem miniaturizing modern electronic devices to allow high speed and high density. Considering the effects in short channel metal oxide semiconductor field transistors (MOSFET), in practice the device is scaled to preserve the long-channel characteristics after miniaturization. Several parameters are chosen and their sensitivity analysis is used for the miniaturization of a MOSFET. The objective is to miniaturize the device in such away to avoid the break down effects at high bias. A finite element based constrained inverse problem methodology is used for the first time for the miniaturization of a MOSFET device.

An improved wide dynamic range silicon photodetector for integration in image sensor arrays

DALSA Inc., Waterloo, Ont., has designed, simulated, and tested a novel silicon photodetector offering several important performance advantages over current industry-standard devices. Currently available imaging devices offered by various manufacturers are typically sensitive to varying light intensity over three orders of magnitude in optical power, while DALSA's novel design offers a logarithmic response of greater than six orders of magnitude in light intensity.Designed to use to advantage the subthreshold effect of short-channel metal oxide semiconductor field effect transistors, the new device is readily integrated into large arrays featuring charge coupled device readout shift registers and metal oxide semiconductor support circuitry. Several devices designed by DALSA incorporating the new detector have been fabricated and tested, including discrete detectors, linear arrays, and area arrays.This paper discusses the theory of operation and performance of an improved wide dynamic range photodetector. Performance considerations include dynamic range, quantum efficiency, noise and noise equivalent power, responsivity, and speed. This photodetector can be integrated to form silicon image sensor arrays. Experimental results will also be presented that demonstrate a maximum-to-minimum detectable light intensity of greater than 106.