Threshold Voltage Shift Research Articles

Scalable Charge-Based Compact Model for Drain Current in Fin-Shaped GaN HEMTs

We present a novel charge-based compact model for drain current in fin-shaped GaN high-electron-mobility transistors (Fin-HEMTs). A positive threshold voltage shift is observed in Fin-HEMTs due to better gate control of the channel. The combined effect of top and side gates on the channel charge density is studied with the help of detailed TCAD simulation. For the first time, a closed-form expression for 2-D electron gas (2-DEG) density in Fin-HEMTs is derived. The fin width dependence of the 2-DEG current is modeled in a unique way by considering the modified gate capacitance and threshold voltage in Fin-HEMTs. The total drain current is modeled as the sum of 2-DEG and double-gate field effect transistor (FET) currents. In addition, the total gate capacitance including the side-gate capacitance for fin structure is also formulated. The model is generic and can be used for different fin geometries using the proposed equivalent circuits as demonstrated. A fin-width-dependent thermal resistance model is proposed and included in the drain current model using a thermal subcircuit. The proposed model is completely analytical and does not require any iteration or fitting parameters in contrast to the available models discussed in the literature. Our model shows excellent agreement with the state-of-the-art experimental data.

Quantitative Analysis of Channel Width Effects on Electrical Performance Degradation of Top-gate Self-aligned Coplanar IGZO Thin-film Transistors under Self-heating Stresses

In this study, a quantitative analysis was conducted on the effects of channel width on electrical performance degradation induced by self-heating stress (SHS) in top-gate self-aligned coplanar indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). From the transfer and capacitance-voltage curves obtained before and after SHS, we revealed that the electrical performance of the TFT was nonuniformly degraded along the channel length direction and the degree of this degradation was more significant in TFTs with a wider channel width. The threshold voltage shift (ΔVSUBTH/SUB) under SHS in the fabricated IGZO TFT was mainly attributed to the increase in the density of shallow donor states and acceptor-like deep states in the IGZO active region and electron trapping into the fast and slow traps in the SiOSUBX/SUB gate dielectric. In addition, we conducted a decomposition of the SHS-induced ΔVSUBTH/SUB originated from each degradation mechanism using the subgap density of states-based ΔVSUBTH/SUB decomposition technique for TFTs with different channel widths. Although every ΔVSUBTH/SUB from each degradation mechanism increased as the channel width increased, increased electron trapping into the slow trap in the SiOSUBX/SUB gate dielectric was the dominant reason for the larger ΔVSUBTH/SUB under SHS in IGZO TFTs with a wider channel width.

Mechanisms of the Device Property Alteration Generated by the Proton Irradiation in GaN-Based MIS-HEMTs Using Extremely Thin Gate Insulator

Recently, we reported that device performance degradation mechanisms, which are generated by the γ-ray irradiation in GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs), use extremely thin gate insulators. When the γ-ray was radiated, the total ionizing dose (TID) effects were generated and the device performance deteriorated. In this work, we investigated the device property alteration and its mechanisms, which were caused by the proton irradiation in GaN-based MIS-HEMTs for the 5 nm-thick Si3N4 and HfO2 gate insulator. The device property, such as threshold voltage, drain current, and transconductance varied by the proton irradiation. When the 5 nm-thick HfO2 layer was employed for the gate insulator, the threshold voltage shift was larger than that of the 5 nm-thick Si3N4 gate insulator, despite the HfO2 gate insulator exhibiting better radiation resistance compared to the Si3N4 gate insulator. On the other hand, the drain current and transconductance degradation were less for the 5 nm-thick HfO2 gate insulator. Unlike the γ-ray irradiation, our systematic research included pulse-mode stress measurements and carrier mobility extraction and revealed that the TID and displacement damage (DD) effects were simultaneously generated by the proton irradiation in GaN-based MIS-HEMTs. The degree of the device property alteration was determined by the competition or superposition of the TID and DD effects for the threshold voltage shift and drain current and transconductance deterioration, respectively. The device property alteration was diminished due to the reduction of the linear energy transfer with increasing irradiated proton energy. We also studied the frequency performance degradation that corresponded to the irradiated proton energy in GaN-based MIS-HEMTs using an extremely thin gate insulator.

A high-reliability scan driver integrated circuit by MO TFTs for a foldable display

Foldable displays have become increasingly used as a solution to the portability-practicality trade-off. A new scan driver integrated with metal oxide thin film transistors (MO TFTs) is proposed for foldable displays to overcome the effects of threshold voltage shifts on the scan driver output. In the scan driver, a feedback section and two series to transistor structures are used to keep the voltage of the key node to sustain a normal output, with this structure, the lower the voltage of the negative supply, the more stable the scan driver will be. Some flexible MO TFTs and 60 stage scan drivers are fabricated by etch stop layer structures on the polyimide substrate. Under different strains and 100 000 times bending with the minimum 3.5 mm bending radius, the characteristics of MO TFTs and the output waveform of the scan driver are measured. Experimental results show that the proposed scan driver shows high reliability since only a little voltage fluctuation occurs at the outputs after the bending test and has a better output waveform with a lower voltage of the negative supply.

Impact of low-dose radiation on nitrided lateral 4H-SiC MOSFETs and the related mechanisms

Lateral type n-channel 4H-SiC metal--oxide--semiconductor field effect transistors (MOSFETs), fabricated using a current industrial process, are irradiated with gamma rays at different irradiation doses in this paper to carry out a profound study on the generation mechanism of radiation-induced interface traps and oxide trapped charges. Electrical parameters (e.g., threshold voltage, subthreshold swing and channel mobility) of the device before and after irradiation are investigated, and the influence of the channel orientation ( and ) on the radiation effect is discussed for the first time. A positive threshold voltage shift is observed at very low irradiation doses (< 100 krad (Si)); the threshold voltage then shifts negatively as the dose increases. It is found that the dependence of interface trap generation on the radiation dose is not the same for doses below and above 100 krad. For irradiation doses < 100 krad, the radiation-induced interface traps with relatively high generation speeds dominate the competition with radiation-induced oxide trapped charges, contributing to the positive threshold voltage shift correspondingly. All these results provide additional insight into the radiation-induced charge trapping mechanism in the SiO2/SiC interface.

Strain relaxation and self-heating effects of fin AlGaN/GaN HEMTs

In this paper, we present a methodology of 3D electro-thermo-mechanical simulation to analyze the strain relaxation and self-heating effects of fin AlGaN/GaN high electron mobility transistors (HEMTs). The free boundaries of narrow fins cause strain relaxation of the AlGaN barrier and a non-uniform strain distribution near the AlGaN/GaN interface. The strain relaxation not only reduces the surface piezoelectric polarization charges (PPCs), but also introduces space PPCs in AlGaN/GaN, leading to a reduction of two-dimensional electron gas density and a positive shift of threshold voltage (V th). The simulated V th shift with fin width agrees well with experimental results from literature. In addition, the inter-fin trenches facilitate more efficient lateral heat spreading and suppress the self-heating effect compared with the planar HEMTs with the same effective gate width.

Improvement of polarization switching in ferroelectric transistor by interface trap reduction for brain-inspired artificial synapses

Numerous devices have been studied to accomplish a brain-inspired neuromorphic computing system; however, their characteristics require improvement to enhance operation accuracy of neuromorphic systems. Here, we propose a ferroelectric field-effect transistor based on Hf0.5Zr0.5O2 for a high-performance artificial synaptic device by reducing interface trap density. Using polarization in the Hf0.5Zr0.5O2 ferroelectric layer, threshold voltage is precisely controlled to achieve synaptic characteristics. However, synaptic characteristics are degraded because interface traps cause threshold voltage shift in the direction opposite to the threshold voltage shift by polarization. Therefore, oxygen plasma treatment was performed to minimize degradation by interface traps. Thus, outstanding synaptic characteristics including the linearity of the weight update, the max/min weight ratio, and the number of weights were observed. Furthermore, high repeatability and long-term plasticity was observed at low operating power. Therefore, our study demonstrated a promising method for implementing a high-accuracy, low-power neuromorphic system with progressed artificial synaptic devices.

Towards Extended Gate Field Effect Transistor-Based Radiation Sensors: Impact of Thicknesses and Radiation Doses on Al-Doped Zinc Oxide Sensitivity

Radiation measurements are critical in radioanalytical, nuclear chemistry, and biomedical physics. Continuous advancement in developing economical, sensitive, and compact devices designed to detect and measure radiation has increased its capability in many applications. In this work, we presented and investigated the performance of a cost-effective X-ray radiation detector based on the extended gate field effect transistors (EGFET). We examined the sensitivity of Al-doped Zinc oxide (AZO) of varying thicknesses, fabricated by chemical bath deposition (CBD), following X-ray irradiation with low and high doses. EGFETs were used to connect samples for their detection capabilities. As a function of the absorbed dose, the response was analyzed based on the threshold voltage shift, and the sensitivity of each device was also evaluated. We demonstrated that thin films are less sensitive to radiation than their disk-type EG devices. However, performance aspects of the devices, such as radiation exposure sensitivity and active dosage region, were found to be significantly reliant on the composition and thickness of the materials used. These structures may be a cost-effective alternative for real-time, room-temperature radiation detectors.

Sensing single domains and individual defects in scaled ferroelectrics.

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors. We electrically measure abrupt threshold voltage shifts and quantify the appearance of new individual defects activated by the ferroelectric switching. Our results show that ferroelectric films can be integrated on heterostructure devices and indicate that the intrinsic electrostatic control within ferroelectric TFETs provides the opportunity for ultrasensitive scale-free detection of single domains and defects in ultra-scaled ferroelectrics. Our approach opens a previously unidentified path for investigating the ultimate scaling limits of ferroelectronics.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In–Ga–Zn–O bilayer channel configuration

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In–Ga–Zn–O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 109), low SS value (180 mV dec−1), and high current drivability (13.6 μA μm−1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm−1 for 104 s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.

Thermal Sensing Characteristics of Low-Voltage n-Channel Organic Field-Effect Transistors With Triple Layers of Naphthalenediimide-Containing Conjugated Polymer and Gate-Insulating Polymers

Organic field-effect transistors (OFETs) were fabricated with n-type naphthalenediimide-based conjugated polymer (N2200) as a channel layer and poly(methyl methacrylate) (PMMA)/poly(vinyl alcohol) (PVA) as a gate-insulating layer. The OFETs with the N2200/PMMA/PVA triple layers were operated with an n-channel mode at low voltages (≤5 V) and their electron mobility reached ca. 0.63 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> at a drain voltage of 5 V. The drain current of OFETs was gradually increased as the temperature of channel region increased from 25 °C to 80 °C, whereas no shift in threshold voltage was measured upon the temperature variation. The relative thermal sensitivity of devices was almost linearly increased with the temperature, while a two-stage behavior by a border of ca. 35 °C was measured for specific thermal sensitivity. The present n-channel OFETs exhibited excellent thermal sensing performances upon repeated approaching/retracting tests using a heat source.

Dual gate AlGaN/GaN MOS-HEMT biosensor for electrical detection of biomolecules-analytical model

This paper proposes an analytical model for a dual gate AlGaN/GaN Metal oxide semiconductor-high-electron-mobility transistor (MOS-HEMT) biosensor for electrical detection of neutral species such as Biotin, Keratin, ChOx, and Zein. When only one subband is occupied and the AlGaN layer is assumed to have been fully ionized, the Fermi–Dirac statistic and 2D state density are used to produce a self-consistent calculation of the carrier density in the quantum well at the interface. It is done by analyzing the impact of biomolecule concentration by inserting a biomolecule of appropriate dielectric permittivity in the cavity area beneath the gate region. The impact of cavity length has been analyzed on the sensor’s performance. The proposed device significantly changes the channel potential, transconductance, drain current, and threshold voltage. Dual gate structures offer superior resistance to short channel effects. Due to enhanced transport characteristics, high carrier mobility, drain current, and a variety of other factors, double gate MOS HEMT outperforms single-gate MOS HEMT. The maximal transconductance, drain on sensitivity, and the maximal drain current that has been attained in this work is 0.017 s, 0.22 and 0.129 mA, respectively, for biomolecule concentration, N b = 3 × 1012. Among all the biomolecules used in this study, Keratin has achieved the maximum shift in threshold voltage and transconductance of 0.4 V and 0.016 s. The increase in current for Keratin, Biotin, Zein, and ChOx is 0.67%, 78%, 17%, and 42%, respectively, from single to dual gate AlGaN/GaN MOS-HEMT. SiO2, Al2O3, and HfO2 oxides have been compared by filling them in the left side of the cavity. Dual gate AlGaN/GaN MOS-HEMT biosensor presents an opportunity to develop robust, low-cost, specific detection and analysis of neutral biomolecule. The analytical model provides good results for drain current according to the comparison of simulation and analytical model findings.

Electrical Reliability of Flexible Low-Temperature Polycrystalline Oxide Thin-Film Transistors Under Mechanical Stress

Electronic devices based on flexible displays have been developed for use in various applications. Upon bending such devices, the applied mechanical force deteriorates the reliability of the devices. Therefore, a high bending reliability that is influenced by tensile and compressive forces that vary depending on the bending radius of curvature must be secured to ensure a reliable device operation. In this study, we investigated the electrical characteristics of flexible low-temperature polycrystalline silicon (LTPS) and amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) on polyimide (PI) substrate and subsequently conducted reliability evaluation of the devices under mechanical stress by applying negative bias temperature illumination stress (NBTIS). The degradations in the electrical properties, such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> ) shift, OFF-state current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {off}}$ </tex-math></inline-formula> ), and subthreshold slope (SS), and reliability, increased, and the reliability worsened, as the tensile force increased under decreasing radius of curvature, whereas relatively low degradation occurred under compressive force. A tensile stress-induced increase in grain boundary state density in polycrystalline silicon (poly-Si) and oxygen vacancy in a-IGZO were verified by density of state (DOS) extraction; the cracks occurring due to tensile stress were optically analyzed; the external moisture penetration along the cracks further degrades the device characteristics. This study provides an analysis of device design for ensuring reliability under the application of mechanical stress, thereby contributing to the development of reliable flexible technology.

Optimizing Photonic Annealing Technique for High-k Dielectric of Full-Solution-Processed Oxide Thin Film Transistor

In this article, it is demonstrated that the photonic annealing process of ultraviolet (UV) irradiation or rapid thermal annealing (RTA)-assisted LA technique can effectively enhance the bias and illumination stability of full-solution-processed oxide thin film transistor (TFT). Although both post-annealing treatments have comparable effects, UV irradiation has relatively less heat loss and time consumption of only 3 min, compared to the RTA process that heats at a temperature of 400 °C and holds 10 min. Depending on the laser annealing (LA)/UV technique, the amorphous hafnium-aluminum oxide (HAO) dielectric thin film exhibits a smooth surface with an rms value of 0.293 nm, a high optical bandgap of 6.19 eV, and good dielectric performance with high dielectric constants of 12.9, low leakage current densities, and high breakdown field of about 4 MV/cm. Moreover, full-solution-processed indium-tin-oxide (ITO)–HAO–tungsten-zinc-tin-oxide (WZTO) TFT shows excellent overall properties with the mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> ) of 10.65 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{2}}\cdot \text{V}^{-{1}}\cdot \text{s}^{-{1}}$ </tex-math></inline-formula> , subthreshold swing (SS) of 198 mV/dec. And the device has good bias and illumination stability, especially the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> ) shifts are all less than 3 V under positive bias illumination stress (PBIS) and negative bias illumination stress (NBIS) testing for 10000 s. These indicate the potential for the photonic annealing process of the UV-assisted LA technique on improving the stability of the full-solution-processed TFTs, which is attributed to high-throughput fabrication for large-area, transparent, and flexible electronics.

Electrically stimulated optical spectroscopy of interface defects in wide-bandgap field-effect transistors

Wide-bandgap semiconductors such as silicon carbide, gallium nitride, and diamond are inherently suitable for high power electronics for example in renewable energy applications and electric vehicles. Despite the high interest, the theoretical limit regarding device performance has not yet been reached for these materials. This is often due to charge trapping in defects at the semiconductor-insulator interface. Here we report a one-to-one correlation between electrically stimulated photon emission and the threshold voltage shift obtained from a fully processed commercial 4H-SiC metal-oxide-semiconductor field-effect power transistor. Based on this observation, we demonstrate that the emission spectrum contains valuable information on the energetic position of the charge transition levels of the responsible interface defects. We etch back the transistor from the reverse side in order to obtain optical access to the interface and record the emitted light. Our method opens up point defect characterization in fully processed transistors after device passivation and processing. This will lead to better understanding and improved processes and techniques, which will ultimately push the performance of these devices closer to the theoretical limit.

Concept of Photoactive Invisible Inks toward Ultralow‐Cost Fabrication of Transistor Photomemories

AbstractFinding the outperforming photoactive charge trapping materials for a new‐trending transistor photomemory application is labor intensive, costly reagents and solvents, and not to mention, inefficient energy and time consumption. In this work, costless organic‐based inks are introduced as a novel photoactive charge storage material that is inspired by high fluorescent ink of cheap invisible pens when exposed to ultraviolet light. The pure powder inks of invisible pens with bright red and greenish‐yellow emission are selected. The estimated usage costs about $0.003 cm−2, confirming its ultralow‐budget material. The pentacene‐based organic field‐effect transistor memory scheme is employed to evaluate the memory behaviors. These invisible‐ink‐based charge storage layers endow a transistor memory device with photoinduced recovery. Interestingly, by conducting the photoassisted operation on the same device, its threshold voltage shifts toward more positive direction, resulting in broaden memory window and faster device operations. On top of that, invisible‐ink‐based transistor photomemory demonstrates the well‐defined and feasible multibit memory cell for the next‐generation storage media. As a result, the employment of commercial invisible inks as a cheapest photoactive charge trapping material can favor the advancement of transistor photomemory devices and related functional applications.

Sub-10 fJ/bit radiation-hard nanoelectromechanical non-volatile memory

With the exponential growth of the semiconductor industry, radiation-hardness has become an indispensable property of memory devices. However, implementation of radiation-hardened semiconductor memory devices inevitably requires various radiation-hardening technologies from the layout level to the system level, and such technologies incur a significant energy overhead. Thus, there is a growing demand for emerging memory devices that are energy-efficient and intrinsically radiation-hard. Here, we report a nanoelectromechanical non-volatile memory (NEM-NVM) with an ultra-low energy consumption and radiation-hardness. To achieve an ultra-low operating energy of less than 10 {{{{{{rm{fJ; bit}}}}}}}^{-1}, we introduce an out-of-plane electrode configuration and electrothermal erase operation. These approaches enable the NEM-NVM to be programmed with an ultra-low energy of 2.83 {{{{{{rm{fJ; bit}}}}}}}^{-1}. Furthermore, due to its mechanically operating mechanisms and radiation-robust structural material, the NEM-NVM retains its superb characteristics without radiation-induced degradation such as increased leakage current, threshold voltage shift, and unintended bit-flip even after 1 Mrad irradiation.

MOCVD-grown β-Ga2O3 as a Gate Dielectric on AlGaN/GaN-Based Heterojunction Field Effect Transistor

We report the electrical properties of Al0.3Ga0.7N/GaN heterojunction field effect transistor (HFET) structures with a Ga2O3 passivation layer grown by metal–organic chemical vapor deposition (MOCVD). In this study, three different thicknesses of β-Ga2O3 dielectric layers were grown on Al0.3Ga0.7N/GaN structures leading to metal-oxide-semiconductor-HFET or MOSHFET structures. X-ray diffraction (XRD) showed the (2¯01) orientation peaks of β-Ga2O3 in the device structure. The van der Pauw and Hall measurements yield the electron density of ~ 4 × 1018 cm−3 and mobility of ~770 cm2V−1s−1 in the 2-dimensional electron gas (2DEG) channel at room temperature. Capacitance–voltage (C-V) measurement for the on-state 2DEG density for the MOSHFET structure was found to be of the order of ~1.5 × 1013 cm−2. The thickness of the Ga2O3 layer was inversely related to the threshold voltage and the on-state capacitance. The interface charge density between the oxide and Al0.3Ga0.7N barrier layer was found to be of the order of ~1012 cm2eV−1. A significant reduction in leakage current from ~10−4 A/cm2 for HFET to ~10−6 A/cm2 for MOSHFET was observed well beyond pinch-off in the off-stage at -20 V applied gate voltage. The annealing at 900° C of the MOSHFET structures revealed that the Ga2O3 layer was thermally stable at high temperatures resulting in insignificant threshold voltage shifts for annealed samples with respect to as-deposited (unannealed) structures. Our results show that the MOCVD-gown Ga2O3 dielectric layers can be a strong candidate for stable high-power devices.

Abnormal Threshold Voltage Shift and Sub-channel Generation in Top-Gate InGaZnO TFTs under Backlight Negative Bias Illumination Stress

Previous reports on the top-gate IGZO thin-film transistors (TFTs) under negative bias illumination stress (NBIS) show a threshold voltage (VTH) shift to the left. However, in the present study, a right shift in VTH was observed in the reverse-sweep current–voltage (I–V) curves after applying NBIS to top-gate IGZO TFTs by a UV backlight. The hysteresis window of the forward and reverse sweep I–V curves widened with the increase in the stress time. The abnormal VTH shift and hysteresis-window increment are explained using an energy-band diagram. In addition, an abnormal gm peak appeared in the forward I–V curve after 2000 s of the backlight NBIS, which was verified by testing the devices with different dimensions. Silvaco TCAD simulation results indicated a strong electric field in the sidewall, confirming the generation of sub-channels. The comparison of the ΔVTH after UV backlight NBIS in three different devices suggested that the higher N2O/SiH4 flow rate and lower power deposition can produce a good quality buffer layer. A rapid examination of a buffer layer is possible using the backlight NBIS. In addition, the presence of H2 in the buffer layer was confirmed by the thermal desorption spectroscopy. Finally, the reliability of the devices can be enhanced by improving the modulation of the existing deposition process.

Focused Review on Print‐Patterned Contact Electrodes for Metal‐Oxide Thin‐Film Transistors

AbstractMetal‐oxide‐semiconductor‐based thin‐film transistors (TFTs) are exploited in display backplanes and X‐ray detectors fabricated by vacuum deposition and lithographic patterning. However, there is growing interest to use scalable printing technologies to lower the environmental impact and cost of processing. There have been substantial research efforts on oxide dielectric and semiconductor materials and their interfaces. Materials for the source/drain (S/D) contact electrodes and their interface to the semiconductor have received less attention, particularly concerning the usage of printing processes. Specific contact resistivity of oxide TFTs with print‐patterned S/D contacts can be 10−2 to 101 Ω cm2, significantly higher than vacuum‐deposited contacts around 10−5 to 10−3 Ω cm2. Problems at the semiconductor/S/D interface, such as large contact resistance, poor adhesion, or cross‐interface contact material migration, affect device characteristics causing hysteresis loops, kink or step‐like distortion, and threshold voltage shift. This work reviews advances in materials and fabrication methods of print‐patterned S/D electrodes for oxide TFTs. Differences in characterization methods among existing literature hamper comparing the performance of print‐patterned S/D contacts. Therefore, systematic and standardized measurements are proposed to assist identification of possible problems, which to some degree can then be mitigated by device fabrication strategies, facilitating well‐performing printed contact electrodes for metal‐oxide TFTs.