Shift Register Research Articles

An efficient Grain-80 stream cipher with unrolling features to enhance the throughput on hardware platform

<span>The stream cipher is a fundamental component of symmetric cryptography and offers unique implementation speed and scalability advantages. Additionally, the complexity of the cipher algorithm deployment environment forces new, appropriate designs and challenges on the already-existing cipher algorithms. To increase throughput, an efficient Grain-80 stream cipher with unrolling features is designed in this manuscript. The Grain-80 cipher uses an 80-bit key, and a 64-bit initialization vector (IV) and contains two feedback shift registers (linear and non-linear) and an output function. The register balancing and unrolling features of the proposed Grian-80 cipher combine to increase throughput while requiring little additional hardware. Low latency, fast throughput, excellent efficiency, and reduced attack susceptibility are all features of the unrolling architecture. The proposed Grain-80 cipher utilizes <1% chip area and operates at 542.7 MHz on Artix-7 field programmable gate array (FPGA). The proposed Grain-80 cipher improves the operating frequency by 14.85% over conventional Grain-80 cipher. The Grain-80 cipher obtains the throughput of 4.35 Gbps and 8.69 Gbps for unrolling factors 8 and 16, respectively. Lastly, the proposed Grain-80 cipher is compared with existing Grain-80 ciphers with improved throughput and hardware efficiency.</span>

A comparative analysis of chaos theory based medical image steganography to enhance data security

The security of patient data is a critical problem for health networks due to the rising popularity of telehealth services and the requirements for clinical data sharing between surgeons, consultants, and medical groups. In contrast to protecting medical data, which includes the cover (i.e., clinical picture), the requirements for protecting other pertinent data are more general. The paper advocates for data encryption before concealment as a robust strategy to uphold patient privacy during medical information exchange. The primary focus of this analysis revolves around a comprehensive exploration of different steganography methods. Through a meticulous examination of various steganographic techniques, including LSB, PVD, and transform domain approaches, this paper provides a detailed analysis of their strengths and limitations. Objective metrics like PSNR and SSIM are employed to dissect the trade-offs between data security and visual fidelity. The research leads to the conclusion that the diagonal queue-based steganog-raphy methodology, supported by chaotic methods, the Linear Feedback Shift Register (LFSR), and the durable Rabin encryption system, is the best course of action. This method enables autonomous data transmission among numerous contacts while ensuring the highest level of confidentiality and integrity of patient data inside e-health networks. In summary, this study provides a comprehensive solution that protects patient data and speeds data transmission inside the expanding framework of e-health networks in order to meet urgent data security concerns in telemedicine and healthcare data exchange.

Evaluation of Image Cryptography by Using Secret Session Key and SF Algorithm

In the unreliable domain of data communication, safeguarding information from unauthorized access is imperative. Given the widespread application of images across various fields, ensuring the confidentiality of image data holds paramount importance. This study centers on the session keys concept, addressing the challenge of key exchange between communicating parties through the development of a random-number generator based on the Linear Feedback Shift Register. Both encryption and decryption hinge on the Secure Force algorithm, supported by a generator. The proposed system outlined in this paper focuses on three key aspects. First, it addresses the generation of secure and randomly generated symmetric encryption keys. Second, it involves the ciphering of the secret image using the SF algorithm. Last, it deals with the extraction of the image by deciphering its encrypted version. The system’s performance is evaluated using image quality metrics, including histograms, peak signal-to-noise ratio, mean square error, normalized correlation, and normalized absolute error (NAE). These metrics provide insights into both encrypted and decrypted images, analyzing the extent to which the system preserves image quality. This assessment underscores the system’s capability to safeguard and maintain the confidentiality of images during data transmission.

Filter generators with increased resistance against algebraic attacks

Filter generators form one of the best known and most studied classes of key stream generators used in synchronous stream ciphers. Each such generator consists of a binary linear shift register with a primitive feedback polynomial and a nonlinear Boolean function, which has a number of requirements related to the condition of generator security against known attacks. One such requirement is the high algebraic immunity of the generator's filter function; this parameter characterises security filter generator against modern algebraic attacks. In certain cases, this requirement is too restrictive in sense of practicality, as it increases the computational or circuit complexity of the key stream generation algorithm. This makes the actuality of increasing the resistance of filter generators with fixed filter functions, that have limited (low) algebraic immunity. The paper proposes to solve this problem by modifying the feedback function of the linear shift register. the security of the proposed generators against algebraic attacks is investigated and is shown that (under certain natural conditions) such generators are more secure at the same initial state length as compared to traditional filter generators. The proposed solution seems to be useful for practical application in advanced hardware-oriented stream ciphers design.

Lightweight encryption with data and device integrity using NLFSR and PUF for the Internet of Medical Things

Nowadays the Internet of Medical Things (IoMT) is in top demand; they communicate with each other in an IoT network, but there are various security issues including privacy preservation, data and device integrity, and authentication. The IoMT devices have challenges like limited computational power and resources, so conventional techniques are not suitable for them. This paper presents a lightweight stream cipher to ensure privacy protection, data integrity, and device integrity using a message authentication code (MAC). The stream cipher is designed using a nonlinear feedback shift register (NLFSR). The cipher is associated with a MAC generated by concatenating a physical unclonable function (PUF) response and the hash of the plaintext to protect the device and data integrity. The use of NLFSR and PUF makes the proposed scheme robust and lightweight for resource-constrained devices like MIoT. To evaluate the quality of the cipher the NIST 800-22 statistical test suite (NIST STS) is used, and results are compared with existing stream ciphers like Rivest cipher 4 (RC4), RC4 based on chaotic mapping (RCCM), and product algebra RCCM (PARCCM). All the tests and comparisons were performed using a Heart Disease Dataset. The scheme ensures the confidentiality and integrity of sensitive medical data which are critical for protecting patient privacy and regulatory compliance. The proposed scheme can also resist cloning attacks on the IoMT devices.

A Response-Feedback-Based Strong PUF with Improved Strict Avalanche Criterion and Reliability.

Physical Unclonable Functions (PUFs) are significant in building lightweight Internet of Things (IoT) authentication protocols. However, PUFs are susceptible to attacks such as Machine-Learning(ML) modeling and statistical attacks. Researchers have conducted extensive research on the security of PUFs; however, existing PUFs do not always possess good statistical characteristics and few of them can achieve a balance between security and reliability. This article proposes a strong response-feedback PUF based on the Linear Feedback Shift Register (LFSR) and the Arbiter PUF (APUF). This structure not only resists existing ML modeling attacks but also exhibits good Strict Avalanche Criterion (SAC) and Generalized Strict Avalanche Criterion (GSAC). Additionally, we introduce a Two-Level Reliability Improvement (TLRI) method that achieves 95% reliability with less than 35% of the voting times and single-response generation cycles compared to the traditional pure majority voting method.

Designing New AES and Implementing it with LFSR Key to Improve Data Security

Data security is an essential aspect of data communication and data storage. The security and confidentiality of the information has become a significant factor in the communication field. To provide high-level security against all kinds of unauthorized accesses, cryptographic algorithms have been applied to various fields such as medical and military applications. Several techniques for encryption and decryption are proposed to promote the security of the communication systems. Most powerful and significant part of the encryption is a key generation. Presently, hackers are able to break the key with help of the modern high computing machines. Advanced Encryption Standard (AES), a symmetric cryptographic algorithm, is acknowledged as the most secure algorithm for the cryptographic process globally. In this work, Novel design and implementation of AES with LFSR (Linear Feedback Shift Register) key for improving data security is presented. The novelty of this work is using LFSR with AES. The Performance of presented approach is evaluated in terms of speed, area and security. The performance of presented technique will provide effective and efficient security to data.

A non-degenerate chaotic bits XOR system with application in image encryption

The existing chaotic systems exhibit chaos degradation phenomena because of the limited chaotic precision in the real number field. In response to this deficiency, this paper proposes a chaotic bits XOR system (CBXS) in the integer field satisfying Devaney’s chaos. That is, CBXS has the property of sensitivity of initial value, topological transitivity, and periodic point density. Then, a series of chaotic and random test results illustrate that the sequences generated by CBXS with linear feedback shift register (LFSR) in the finite field GF(2) have good random and chaotic performance. It can overcome the chaos degradation problem because it is generated in the integer field and can avoid the limited precision in the real number field. Finally, we employ the proposed CBXS to image encryption with the optimized Arnold’s transformation. The experimental results verify that even after simple encryption, the cipher image still exhibits good encryption effect and efficiency, which illustrates the effectiveness of CBXS.

A secure scan architecture using dynamic key to thwart scan-based side-channel attacks

Scan testing is widely used in the rigorous testing of modern integrated circuits. However, the controllable and observable nature of the scan design also provides opportunities for attackers who can utilise this structure to steal secret information stored in the chip. This paper proposes a secure Design for Testability (DFT) architecture to prevent scan-based attacks. The scheme uses a modified Linear Feedback Shift Register (LFSR) to dynamically generate keys for the scan design key generator and verifies them against a specific selection of test key flip-flops in the original scan chain, and locks the control signals by transmitting the outputs of the verification comparisons to a OR gate. When the test authorisation key is correct, the circuit performs a normal scan operation; otherwise, the circuit enters an abnormal test mode and the data in the scan chain is dynamically obfuscated, thus preventing from observing valid data or deriving an encryption key through the output of the scan chain.

Above and below: The sounding of haunted geologies

This article investigates uses of sound in contemporary artists’ time-based work in relation to Nils Bubandt’s concept of ‘haunted geologies’. The work of artists and filmmakers such as Ben Rivers, Derek Jarman, Mark Jenkin, Shift Register and Louise K. Wilson is utilized as a means of exploring and enriching the concept of the haunted geological. Combined uses of field recording, post-production and the manipulation of frequencies are examined, as suggestive of affective acts of divination and evocation, which evidence both visual and sonic signification. The visible forms and discrete voids of ‘difficult’ and unquiet locations (in the United Kingdom and Australia) that have been disturbed, unsettled or remain resistant to knowledge provide the focus for a discussion, appertaining both to the realm of the ‘above’ and to the ‘below’. The concept of ghost strata enables a consideration or navigation of that which has been misplaced, providing a useful and productive means for imaginative reflection on the impacts of loss. While suggesting this loss, nonetheless, ghost strata remind us of the persistence of stone as a form of vibrant and sentient matter – providing evidence of material agency which foregrounds and heightens the sense of the destructive nature of the current environment. The potency of materiality is further present in the media utilized to ‘capture’ or co-create phenomena across a variety of scales and states of rock and stone. To this end, the powers of analogue film, audio recorder or hard drive to both document and manifest phenomena are explored as a means of unearthing a recent past of spectrality in the geologic. In this sense, the ghosts that we have created can be seen to foretell of future hauntings in the time of the Anthropocene.

Accuracy Analysis on Design of Stochastic Computing in Arithmetic Components and Combinational Circuit

Stochastic circuits are used in applications that require low area and power consumption. The computing performed using these circuits is referred to as Stochastic computing (SC). The arithmetic operations in this computing can be realized using minimum logic circuits. The SC system allows a tradeoff of computational accuracy and area; thereby, the challenge in SC is improving the accuracy. The accuracy depends on the SC system’s stochastic number generator (SNG) part. SNGs provide the appropriate stochastic input required for stochastic computation. Hence we explore the accuracy in SC for various arithmetic operations performed using stochastic computing with the help of logic circuits. The contributions in this paper are; first, we have performed stochastic computing for arithmetic components using two different SNGs. The SNGs considered are Linear Feed-back Shift Register (LFSR) -based traditional stochastic number generators and S-box-based stochastic number generators. Second, the arithmetic components are implemented in a combinational circuit for algebraic expression in the stochastic domain using two different SNGs. Third, computational analysis for stochastic arithmetic components and the stochastic algebraic equation has been conducted. Finally, accuracy analysis and measurement are performed between LFSR-based computation and S-box-based computation. The novel aspect of this work is the use of S-box-based SNG in the development of stochastic computing in arithmetic components. Also, the implementation of stochastic computing in the combinational circuit using the developed basic arithmetic components, and exploration of accuracy with respect to stochastic number generators used is presented.

Josephson junction oscillator embedded in the microcontroller: Pseudo-random number generation and combination synchronization

Dynamical scrutiny of the resistive capacitive inductive shunted Josephson junction (JJ) oscillator (RCLSJJO), microcontroller realization, pseudo-random number generation (PRNG) and combination synchronization are achieved in this paper. Numerical probing led to the establishment that the RCLSJJO is characterized by regular behaviors, bistable periodic-2-oscillations, periodic bursting characteristics and various shapes of chaotic dynamics. Thereafter, the vast dynamical characteristics obtained theoretically are realized by the microcontroller realization with qualitative agreements. Moreover, a chaos-based PRNG is designed by using chaotic RCLSJJO and linear feedback shift register (LFSR) as post-processing unit. Satisfactory results are obtained from the NIST 800–22 test suite and the randomness of binary data generated from the proposed RCLSJJO-based PRNG is confirmed for chaos-based digital applications. Lastly, the combination chaos synchronization of two drive and one response RCLSJJO is proven thanks to the theoretical analysis.

Position error-free control of magnetic domain-wall devices via spin-orbit torque modulation

Magnetic domain-wall devices such as racetrack memory and domain-wall shift registers facilitate massive data storage as hard disk drives with low power portability as flash memory devices. The key issue to be addressed is how perfectly the domain-wall motion can be controlled without deformation, as it can replace the mechanical motion of hard disk drives. However, such domain-wall motion in real media is subject to the stochasticity of thermal agitation with quenched disorders, resulting in severe deformations with pinning and tilting. To sort out the problem, we propose and demonstrate a new concept of domain-wall control with a position error-free scheme. The primary idea involves spatial modulation of the spin-orbit torque along nanotrack devices, where the boundary of modulation possesses broken inversion symmetry. In this work, by showing the unidirectional motion of domain wall with position-error free manner, we provide an important missing piece in magnetic domain-wall device development.

Random Switching Period SVPWM Technique with Variable Sampling Frequency for Three‐Phase Power Converters

To improve the pulse width modulation (PWM) harmonic suppression effect of the three‐phase VSI‐fed PMSM system, this paper proposed a novel random switching period (RSP)‐Space Vector Pulse Width Modulation (SVPWM) technique for the three‐phase power converter. First, the proposed technique replaces the 10‐bit linear feedback shift register pseudorandom number generator (LFSR‐PRNG) with a Tiny Mersenne Twister (MT)‐PRNG to quickly generate high‐quality pseudorandom number sequences. Then, to reduce the sampling error caused by the current ripple, this paper analyzes the sampling timing under different modulation techniques. Based on the interrupted update mechanism of the Infineon AURIX‐TC264, the variable frequency sampling of the RSP‐SVPWM technique is implemented to ensure the best sampling of the motor phase current. Finally, the simulation and experimental results show that the proposed technique can effectively disperse PWM harmonic energy. Meanwhile, the RSP‐SVPWM technique based on variable sampling frequency effectively improves the phase current quality of the PMSM system. The proposed technique shows great potential for suppressing PWM harmonics in integrated PMSM systems. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers

True random number generators (TRNGs), as an important component of security systems, have received a lot of attention for their related research. The previous researches have provided a large number of TRNG solutions, however, they still failed to reach an excellent tradeoff in various performance metrics. This article presents a shift-registers metastability-based TRNG, which is implemented by compact reference units and comparison units. By forcing the D flip-flops in the shift-registers into the metastable state, it optimizes the problem that the conventional metastability entropy sources consume excessive hardware resources. And a new method of metastable randomness extraction is used to reduce the bias of metastable output. The proposed TRNG is implemented in Xilinx Spartan-6 and Virtex-6 FPGAs, which generate random sequences that pass the NIST SP800-22, NIST SP800-90B tests and show excellent robustness to voltage and temperature variations. This TRNG can consume only 3 slices of the FPGA, but it has a high throughput rate of 25 Mbit/s. In comparison with state-of-the-art FPGA-compatible TRNGs, the proposed TRNG achieves the highest figure of merit FOM, which means that the proposed TRNG significantly outperforms previous researches in terms of hardware resources, throughput rate, and operating frequency tradeoffs.

Test Compression for Launch-on-Capture Transition Fault Testing

A new low-power test compression scheme, called Dcompress , is proposed for launch-on-capture transition fault testing by using a new seed encoding scheme, a new design for testability architecture, and a new low-power test application procedure. The new seed encoding scheme generates seeds for all tests by selecting a primitive polynomial that encodes all tests of a compact test set. A software-defined linear feedback shift register architecture, called SLFSR , is proposed to make the new method conform to the current flow of design and test. Experimental results on benchmark circuits show that test data volume can be compressed up to 6300X with the well-compacted baseline test set for a design with 11.8M gates and more than 1.1M scan flip-flops.

Self-Clocked Shift Registers Utilizing 90 nm CMOS: Design, Analysis and Insights

This paper presents an efficient approach to designing and analyzing four bit shift register utilizing self-clocked D flip-flops as integral storage components. The use of internal clock generation within these flip-flops obviates the need for external clock synchronization. These specially designed flip-flops incorporate a reduced number of transistors in comparison to conventional designs, leading to notable enhancements in power efficiency, packaging density, and operational speed. The implementation of self-triggered D flip-flops facilitates the creation of various shift register configurations, including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial out (PISO), and Parallel in Parallel out (PIPO). These registers not only occupy a smaller die area but also exhibit diminished power consumption and heightened operational speed when contrasted with standard counterparts. The design and simulation procedures are executed using the Microwind tool and a 90 nm CMOS technology.

Hybrid FCSR Based Stream Cipher for Secure Communications in IoT

<p>Linear Feedback Shift Register (LFSR) is the basic hardware of stream cipher, and Feedback with Carry Shift Register (FCSR) is the nonlinear analogues of LFSR. FCSR is a feedback architecture to generate long pseudorandom sequence. In this paper, we study the characteristics of FCSRs combined with nonlinear circuits such as Dawson’s Summation Generator (DSG), lp-Geffe generator and etc. Then we proposed a hybrid FCSR applying DSG and lp-Geffe generator as nonlinear combining elements to increase the period and the linear complexity of the output sequence. In addition, we further investigate the period, linear complexity, randomness, and use known attacks to verify the security strength of the proposed keystream generator. The pass rates of the proposed scheme are 100% for FIPS PUB 140-1 random tests, and at least 98% for SP800-22 random test, respectively.</p> <p> </p>

Research on the current compensation mechanism of FJTL in ERSFQ

Energy-efficient rapid single flux quantum (ERSFQ) devices have unique energy advantages with a power consumption of less than 0.001fJ per single-bit switch, even considering the energy required for the refrigeration system, achieving ultra-low energy consumption of sub-fJ/bit. Combined with its typical operating frequency in the tens of GHz range, ERSFQ circuits have the potential to realize computing chips with extremely high computational power and energy efficiency, making them highly promising for applications in the post-Moore era. However, the performance improvement of ERSFQ circuits faces two challenges. One is how to reduce the size of their feeding Josephson transmission line (FJTL), which is required to stabilize the voltage bias of the ERSFQ circuits. The second challenge is how to improve their bias margin. The measured bias margin of ERSFQ circuits is relatively smaller than for Rapid Single Flux Quantum (RSFQ) circuits. This study investigates the current compensation mechanism of the FJTL and derives a formula for the compensating current ΔI in the main logic circuit by each pulse input to the FJTL. Based on the formula, a method is proposed to enhance the bias margin of ERSFQ circuits while reducing the size of FJTL by applying feeding pulses into the FJTL. We applied this method to an 8-bit ERSFQ shift register (SR), where the size of its FJTL is 4 JTLs (each JTL consists of 2 Josephson junctions). The measurement demonstrated an improvement of the bias margin from [84 %, 104 %] to [38 %, 104 %], confirming the feasibility of the proposed method. Furthermore, by comparing the measurement results of an 8-bit ERSFQ SR, where the size of its FJTL is 6 JTLs, it is demonstrated that applying this method can also reduce the size of the FJTL while maintaining a large margin.

High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.