Self-Clocked Shift Registers Utilizing 90 nm CMOS: Design, Analysis and Insights

Abstract

This paper presents an efficient approach to designing and analyzing four bit shift register utilizing self-clocked D flip-flops as integral storage components. The use of internal clock generation within these flip-flops obviates the need for external clock synchronization. These specially designed flip-flops incorporate a reduced number of transistors in comparison to conventional designs, leading to notable enhancements in power efficiency, packaging density, and operational speed. The implementation of self-triggered D flip-flops facilitates the creation of various shift register configurations, including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial out (PISO), and Parallel in Parallel out (PIPO). These registers not only occupy a smaller die area but also exhibit diminished power consumption and heightened operational speed when contrasted with standard counterparts. The design and simulation procedures are executed using the Microwind tool and a 90 nm CMOS technology.