Adiabatic logic based shift registers for low energy IoT architecture—Design and contemplation

Abstract

AbstractShift register is one of the important components in any digital circuit. By improving the performance of shift register, one can improvise the whole system performance. Shift registers are the basic memory units and data transfer devices in IoT applications. The efficacy of computing devices depends on the performance of arithmetic circuits, including shift registers. Adiabatic logic has been proposed as anew computing platform to develop power‐efficient IoT devices. This paper presents low power adiabatic shift registers. The design of shift registers uses D flipflop, based on DC‐DB PFAL (direct‐current diode based positive feedback adiabatic logic). Performance parameters of the presented circuits are analyzed for transistor count, power dissipation, latency, and PDP (power delay product). Simulations are run for all the presented circuits at 180nm and 45nm technology nodes. It is found that the proposed parallel in parallel out shift register (PIPO) design outperforms with the improvement in PDP as 53%, 53%, and 57% compared to theserial in serial out (SISO), serial in parallel out (SIPO), and parallel inserial out (PISO) shift registers respectively at 100MHz and 45 nm technology node. Further, the proposed PIPO shift register shows improved performance than the other designs in the literature.