Voltage Shift Research Articles

High-mobility InSnZnO Thin Film Transistors via Introducing Water Vapor Sputtering Gas.

There is always a doubt that introducing water during oxide growing has a positive or negative effect on the properties of oxide films and devices. Herein, a comparison experiment on the condition of keeping the same oxygen atom flux in the sputtering chamber is designed to examine the influences of H2O on In-Sn-Zn-O (ITZO) films and their transistors. In comparison to no-water films, numerous unstable hydrogen-related defects are induced on with-water films at the as-deposited state. Paradoxically, this induction triggers an ordered enhancement in the microstructure of the films during conventional annealing, characterized by a reduction in H-related and vacancy (Vo) defects as well as an increase in film packing density and the M-O network ordering. Ultimately, the no-water thin-film transistors (TFTs) exhibit nonswitching behavior, whereas 5 sccm-water TFT demonstrates excellent electrical performance with a remarkable saturation field-effect mobility (μFE) of 122.10 ± 5.00 cm2·V-1·s-1, a low threshold (Vth) of -2.30 ± 0.40 V, a steep sub-threshold swing (SS) of 0.18 V·dec-1, a high output current (Ion) of 1420 μA, and a small threshold voltage shift ΔVth of -0.77 V in the negative bias stability test (3600 s).

Polymer-Chain Aggregation-induced Electrical Gating at the H- and J-aggregate P3HT

This research explores how aggregation influences the electrical behavior at both the planar - heterojunction poly(3-hexylthiophene) (P3HT)/SiO2 and P3HT/ZnO nanocrystal (NC) interfaces. The formation of H- and J-type aggregates leads to distinct molecular ordering and packing structures, manifesting as changes in threshold voltage shifts (electrical gating) as well as absorption and luminescence properties. Ultrasound irradiation (sonication) significantly alters the molecular arrangement in P3HT, favoring the formation of H-aggregates over the typically formed J-aggregates. In pristine P3HT, J-aggregates facilitate efficient exciton movement and electrical generation, resulting in higher photocurrents compared to sonicated-P3HT, which predominantly forms H-aggregates. Field-effect transistors (FETs) based on sonicated P3HT exhibit a more positive threshold voltage and increased mobility, indicating the presence of more mobile charge carriers, even in the absence of an applied voltage. In interfaces with ZnO NC, pristine P3HT demonstrates a considerable shift in threshold voltage under illumination, attributed to electron trapping. Conversely, sonicated P3HT interfaced with ZnO NC shows less electron trapping and minimal change in threshold voltage. This study underscores how the type of aggregate (H or J) in P3HT significantly dictates light-induced electrical gating. Ultrasound irradiation (sonication), while enhancing mobility by improving crystallinity, leads to a decrease in photocurrent efficiency in H-aggregates compared to the J-aggregates present in pristine-P3HT.

Performance evaluation of polycrystalline Si1−xGex thin-film transistors fabricated by continuous-wave laser lateral crystallization on glass substrates

This study was aimed at elucidating the performance of continuous-wave laser lateral-crystallized (CLC) polycrystalline Si1−xGex (poly-Si1−xGex) thin-film transistors (TFTs). The transfer characteristics of the n-ch CLC poly-Si1−xGex TFTs (x = 0, 0.05, 0.1, and 0.3) exhibited a positive shift in the threshold voltage (Vth) with increasing Ge content. Furthermore, the off-current in the p-ch CLC poly-Si0.9Ge0.1 TFTs decreased with decreasing film thickness. These properties of the CLC poly-Si1−xGex TFTs can be attributed to the generation of acceptors and increment of gate SiO2/poly-Si1−xGex interface charge state with increasing Ge content. The generation of acceptors was also supported by Hall effect measurements. In addition, the thermal stability of acceptors up to 700 °C was elucidated through Hall effect measurements and TFT performance evaluations. Furthermore, we examined the origins of these acceptors. This experiment highlighted the sensitivity of Si1−xGex to Ge incorporation, even in small amounts.

A Common Source 3D FeFET with Disturb Inhibition Program and Erase Method

A common source p-type single-crystal channel three-dimensional ferroelectric field-effect transistor (3D FeFET) in a 2 × 2 × 3 array is proposed. Two programming and erasing conditions are introduced. A large memory window (>1.2 V), good retention (>10 years), and high speed (<100 ns) was presented under high voltage (±6 V) conditions. The endurance, >103, was observed under relatively low voltage (±3 V) conditions. Based on these two conditions, a novel asymmetric bias program and erase method is proposed to obtain good disturb inhibition. A more than 0.5 V threshold voltage shift in target cell was achieved while threshold voltage shift in unselected cell was limited, and analysis of long term disturb in novel method is proposed, showing good disturb inhibition. Additional investigation in word line disturbance shows causation and efficiency of disturb. Building upon the proposed structure of the 3D FeFET array, a vector matrix multiplication able to calculate 2-bit weights was designed and demonstrated. This work provides a potential solution for increasing integration density with 3D FeFET array.

97‐1: Late‐News Paper: Mechanism for the Irreversible Threshold Voltage Behavior by Polyimide Charging in Thin Film Transistors

The irreversible threshold voltage (Vth) shift by polyimide (PI) charging is experimentally demonstrated. The Vth of device without PI electrode is positively moved during the release. Interestingly, the shifted Vth is not recovered to initial value up to one month. The mechanism for the irreversibility is suggested.

P‐14: High Mobility and High Light Stability Oxide Back‐Channel‐Etched TFT and Application to High‐End LCD NB Production

A high mobility (29 cm2 /Vs) and high light stability oxide thin‐film transistor (TFT) with 8 mask back channel etched (BCE) structure has been fabricated. Remarkable enhancement in negative gate‐bias thermal stress with illumination has been achieved, resulting in a threshold voltage (Vth) shift of ‐0.01 V after 1 hour. A 16.0 inch WQHD 240Hz LCD NB has been developed using high mobility and high light stability oxide TFT in G8.5.

P‐25: Tailoring the Threshold Voltage Control of Oxide Thin‐Film Transistor by Controlling Electron Injection using PN Semiconductor Heterojunction Structure

The threshold voltage (VT) is the most important parameter in semiconductor devices. To control the VT of the thin‐film transistors (TFTs), we propose heterojunction structure of p‐type Tellurium (Te) and n‐type Aluminum‐Doped Indium‐Zinc‐Tin‐Oxide (Al:IZTO) which acts as electron blocking layer and carrier transporting layer, respectively. We investigate the effect of adding the heterojunction layer on the Al:IZTO and demonstrate VT shift up to +20V by adjusting the thickness and single / double deposition of the heterojunction Te layer.

P‐13: Excessive Oxygen induced Threshold Voltage Shifts in High Mobility Top‐Gate PrIZO TFTs

The top gate self‐alignment (TGSA) Praseodymium‐doped indium zinc oxide (PrIZO) thin film transistor (TFT) was fabricated with different process condition in our production line, and high field effect mobility of 40.83 cm2 V‐1 s‐1 was obtained by regulating the GI and ILD parameters. At the same time, the devices show excellent stability with PBTS of 0.52 V and NBTIS of ‐0.9 V, indicating its potential in overcoming the trade‐off between mobility and reliability.

P‐11: High Mobility BCE Oxide TFT Technology for Demux Driving Notebook LCD

Ln‐IZO based target was employed to deposit as a channel layer in amorphous Ln‐In‐Zn‐O thin‐film transistors. Here, we use the carrier/barrier bilayer stacked AOS TFTs to improve the mobility and stability. High mobility Ln‐oxide is for better charge transport. The barrier layer is fine‐tuned for better reliability. After optimization of the stacked structure of the active layer and the parameters of the PV SiO2 layer, the devices exhibited superior electric properties. The device shows high mobility (35.4 cm2/Vs) and small voltage shifts (1.1/‐1.5 V) of PBTS (positive bias temperature stress) and NBTIS (negative bias temperature illumination stress). We fabricated a 14 inch notebook liquid crystal display (LCD) with the Demux 1:3 circuit design using the high performance bilayer stacked TFTs.

39‐1: Invited Paper: An Improved Gate Driver Using Oxide TFTs for Large OLED Displays

In this paper, we present the small area and high reliable gate driver in panels using a‐IGZO TFTs for large OLED displays. The proposed gate driver circuit has a small area structure with multiple output buffers connected to one shift register circuit. To lower the voltage stress of the pull‐down TFTs, which have the highest voltage stress among the TFTs of the gate driver, the initial voltage of those TFTs is set to low and increases according to the threshold voltage shift of TFTs during operation. It could be implemented by sensing the degradation of the TFTs using the programmable DC driving method. With these technologies, we were able to reduce the gate driver design area by 40% and improve the reliability by 30% despite reducing the circuit area. We successfully developed OLED TVs from 42 inches to 97 inches using the proposed gate driver.

10‐4: Late‐News Paper: Precise Compensation of Device Variability in IGZO‐based Ferroelectric Thin‐Film Transistors for Enhanced Transparent Display Performance

We demonstrate the compensation of device‐to‐device variation in threshold voltage using programmable ferroelectric indium‐gallium‐zinc‐oxide thin‐film transistors. Furthermore, degradationinduced threshold voltage shift can be mitigated by programming, setting the characteristics back to their pristine state. This can be a promising alternative for the replacement of complex VT compensation circuits in display applications.

Interfacial Charge Transport Enhancement of Liquid-Crystalline Polymer Transistors Enabled by Ionic Polyurethane Dielectric.

In organic field-effect transistors (OFETs) using disordered organic semiconductors, interface traps that hinder efficient charge transport, stability, anddevice performance are inevitable. Benchmark poly(9,9-dioctylfuorene-co-bithiophene) (F8T2) liquid-crystalline polymer semiconductor has been extensively investigated for organic electronic devices due to its promising combination of charge transport and light emission properties. This study demonstrates that high-capacitance single-layered ionic polyurethane (PU) dielectrics enable enhanced charge transport in F8T2 OFETs. The ionic PU dielectrics are composed of a mild blending of PU ionogel and PU solution, thereby forming a solid-state film with robust interfacial characteristics with semiconductor layer and gate electrode in OFETs and measuring high capacitance values above 10 µF cm-2 owing to the combined dipole polarization and electric double layer formation. The optimized fabricated ionic PU-gated OFETs exhibit a low-voltage operation at -3V with a remarkable hole mobility of over 5 cm2 V-1 s-1 (average = 2.50 ± 1.18 cm2 V-1 s-1), which is the highest mobility achieved so far for liquid-crystalline F8T2 OFETs. This device also provides excellent bias-stable characteristics in ambient air, exhibiting a negligible threshold voltage shift of -0.03V in the transfer curves after extended bias stress, with a reduced trap density.

Facile routes to enhance doping efficiency using nanocomposite structures for high-mobility and stable PEALD-ITGO TFTs

In–Sn–Ga–O (ITGO) thin-film transistors (TFTs) fabricated by atomic layer deposition (ALD) are promising candidates for widespread semiconductor applications because of their high mobility and stability. To further improve the device characteristics, the doping efficiency of each cation must be increased. Here, we propose a facile method to enhance the device characteristics using plasma-enhanced ALD-nanocomposite (NC) structures. The deposition of SnO2 materials within the In2O3 layer of the ITGO film with the NC-ITO structure accelerates the reduction of In2O3 (In0: 35.3 % →46.1 %), thereby stabilizing SnO2 (Sn4+: 71.0 % →89.1 %). In addition, this process significantly decreases the fraction of oxygen-related defects (Odefect: 24.0 % →17.6 %) because Sn–O has a substantially higher bond dissociation energy than In–O. Consequently, the ITGO TFT with the NC-ITO active layer exhibits considerable improvements in the electrical parameters, such as an increase in the field-effect mobility from 41.9 to 54.5 cm2/V s and an enhancement in the subthreshold swing from 69.8 to 64.8 mV/decade. In addition, the device shows excellent results for negative bias illumination stress and positive bias temperature stress, with the differences in the threshold voltage shift being −0.22 and + 0.06 V, respectively.

E-Mode AlGaN/GaN HEMTs Using p-NiO Gates

Sputtered p-NiO films were used to suppress gate leakage and produce a positive shift in gate voltage of AlGaN/GaN high electron mobility transistors for e-mode operation. A direct comparison with Schottky gate devices fabricated on the same wafer shows the utility of the NiO in increasing the on-off ratio and shifting the threshold voltage from -0.95 V (Schottky gated) to +0.9 V (NiO gated). The breakdown voltage was 780 V for a 40 µm drain-source separation. The sub-threshold swing decreased from 181 mV/dec for Schottky gate HEMTs to 128 mV/dec on NiO-gated devices. The simple fabrication process without any annealing or passivation steps shows the promise of NiO-gates for e-mode AlGaN/GaN HEMT operation.

Evidence‐Based Understanding of Lateral Hole Transport During OFF‐State Stress Completing Dynamic GaN‐on‐Si Buffer Charging Model

Gallium nitride (GaN)‐on‐Si high electron mobility transistors require insulating GaN buffers, which are prone to charge trapping and result in dynamic ON‐state resistance (dR DS,on) that negatively impacts performance and reliability. Herein, simultaneous measurements of threshold voltage shift (dV TH) and dR DS,on during OFF‐state stress with microsecond time resolution are employed. Ohmic p‐GaN gate contacts enable the use of dV TH to probe charge accumulation under the gate, while dR DS,on probes charge accumulation in the gate‐drain access region. Comparison of dV TH and dR DS,on provides direct evidence of lateral hole transport in the GaN buffer when exposed to a lateral electric field in OFF‐state. This lateral hole transport causes positive charge accumulation in the buffer under the gate and triggers a newly proposed electron injection mechanism into the same region. Only by considering the combination of lateral hole transport and electron injection under the gate the observed up to fivefold dR DS,on increase in OFF‐state stress compared to back‐gating at low biases can be explained. Furthermore, another electron spillover mechanism is introduced that occurs for large positive charge accumulation under the gate and limits the maximum negative dV TH. All known and newly introduced processes during OFF‐state are summarized in a concise dynamic buffer charging model.

Density functional model of threshold voltage shifts at High-K/Metal gates

A density functional analysis of oxide dipole layers used to set the threshold voltages in high-K/metal CMOS gate stacks is given in terms of the band alignments and chemical trends of these component oxide layers. The oxides SrO, La2O3, HfO2 and Al2O3 are found to have similar band gaps and form a ‘staircase’ of band alignments, allowing them to shift the metal electrode Fermi level in both n-type and p-type directions. This analysis supersedes previous largely empirical models based on metal oxide ion densities or electronegativity scales.

A Theoretical Approach to Study the Frequency Dependent Dielectric behavior of Breast Cancer Cells using AlN buffer-based AlGaN/GaN HEMT

Abstract This article investigates the applicability of open gated high electron mobility transistor (HEMT) as a biosensing platform for Breast cancer detection. The present study reports the detection of healthy (MDA-10) and malignant cells (MDA-MB-231) associated with breast cancer using high-quality AlN buffer AlGaN/GaN HEMT with dual cavity structure formed by etching out the gate metal from source and drain sides under the gate region. The AlN buffer AlGaN/GaN HEMT provides better 2DEG confinement and large conduction band offset than GaN buffer. The proposed design is analyzed at frequencies of 900 MHz and 10 GHz, as breast cells have distinct dielectric properties at different microwave frequencies. The variation in dielectric constant of the cavity region corresponding to biomolecular species will change the device’s electrical characteristics and hence can be used to detect breast cancer cells. In this work, the device sensing parameters considered for analysis are shift in threshold voltage and drain current sensitivity. The device performance has also been analyzed by optimizing cavity thickness and length to select the best design for the sensing. The effect of non-ideal conditions such as steric hindrance and probing is also studied by emulating these real time effects in simulation. The device shows a maximum drain current sensitivity of 29.94% for 20 nm of cavity thickness and 1µm of the cavity length. The results depict that the proposed device design exhibits a highly sensitive response and can be promising alternate for future biosensing applications.

SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆Vth) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (Crss), while maintaining a similar low ON-resistance.

Enhanced stability in InSnO transistors via ultrathin in-situ AlOx passivation

In this study, we present the impact of an ultrathin in-situ AlOx passivation layer on the electrical performance and stability of InSnO (ITO) transistors. Devices incorporating an ultrathin (∼2 nm) AlOx passivation layer demonstrate satisfactory electrical performance and stability, characterized by a decent field-effect mobility, enhancement mode operation, notably reduced subthreshold swing, negligible hysteresis, and, notably, a significantly reduced threshold voltage shift under negative bias stress (NBS) and positive bias stress (PBS), respectively. The total trap density (Ntot), extracted through the sub-threshold slope, and the trap density (Nt), measured using low-frequency noise (LFN) for the AlOx-passivated ITO transistors, are significantly decreased. Those improvements can be attributed to the suppression of oxygen vacancy formation during the reactively-sputtered AlOx and subsequent annealing processes, as demonstrated by comparing the in-depth X-ray photoelectron spectroscopy (XPS) results of the AlOx-passivated and un-passivated ITO films. These results underscore the potential of in-situ reactively-sputtered ultrathin AlOx passivation layers to enhance the stability of thin-film transistors with In-rich channels.

Influence of electrical field on the susceptibility of gallium nitride transistors to proton irradiation

Radiation susceptibility of electronic devices is commonly studied as a function of radiation energetics and device physics. Often overlooked is the presence or magnitude of the electrical field, which we hypothesize to play an influential role in low energy radiation. Accordingly, we present a comprehensive study of low-energy proton irradiation on gallium nitride high electron mobility transistors (HEMTs), turning the transistor ON or OFF during irradiation. Commercially available GaN HEMTs were exposed to 300 keV proton irradiation at fluences varying from 3.76 × 1012 to 3.76 × 1014 cm2, and the electrical performance was evaluated in terms of forward saturation current, transconductance, and threshold voltage. The results demonstrate that the presence of an electrical field makes it more susceptible to proton irradiation. The decrease of 12.4% in forward saturation and 19% in transconductance at the lowest fluence in ON mode suggests that both carrier density and mobility are reduced after irradiation. Additionally, a positive shift in threshold voltage (0.32 V and 0.09 V in ON and OFF mode, respectively) indicates the generation of acceptor-like traps due to proton bombardment. high-resolution transmission electron microscopy and energy dispersive x-ray spectroscopy analysis reveal significant defects introduction and atom intermixing near AlGaN/GaN interfaces and within the GaN layer after the highest irradiation dose employed in this study. According to in-situ Raman spectroscopy, defects caused by irradiation can lead to a rise in self-heating and a considerable increase in (∼750 times) thermoelastic stress in the GaN layer during device operation. The findings indicate device engineering or electrical biasing protocol must be employed to compensate for radiation-induced defects formed during proton irradiation to improve device durability and reliability.