Shallow Trench Isolation Corner Research Articles

Hot-Carrier-Induced On-Resistance Degradation of n-Type Lateral DMOS Transistor With Shallow Trench Isolation for High-Side Application

In this paper, the hot-carrier-induced on-resistance degradation of the n-type lateral DMOS (nLDMOS) transistor with shallow trench isolation (STI) for high-side application has been experimentally investigated. We have found that the dominant on-resistance degradation mechanism of the high-side nLDMOS device (HS-nLDMOS) is the interface state generation at the STI corner. Moreover, the degradation of the on-resistance for high-side application (R on,hs, measured at high drain voltage and high source voltage) is much larger than that for low-side application (R on,ls, measured at low drain voltage and grounded source). This is because the current distribution under the R on,hs state is closer to the damaged STI corner than that under the R on,ls state due to the larger potential difference between the drain and the substrate. Therefore, the on-resistance degradation of the HS-nLDMOS must be measured by using the R on,hs condition, to evaluate the lifetime of the device accurately.

Investigation of STI edge effect on programming disturb in localized charge trapping SONOS flash memory cells

Abstracts The impact of shallow trench isolation (STI) on non-volatile memories has become much more serious for sub-90-nm CMOS technologies. This paper uses the localized charge trapping polysilicon-oxide-nitride-oxide-silicon (SONOS) flash memory cells to investigate STI edge effect on programming disturb when the channel hot electron injection programming method is applied. The different programming disturbs between the central cells far from STI and the edge cells close to STI are experimentally presented on the array level. At the programmed state, the edge cells suffer larger decrease of threshold voltage compared to the central cells under the same drain disturb. However, both edge and central cells at the erased state have not any significant variations of threshold voltage distribution under the same disturb conditions. In addition, both edge and central cells demonstrate almost the same behaviors under gate disturb. Two-dimension process simulation results show that the edge cells suffer a higher compressive stress caused from STI corner than the central cells. The higher compressive stress increases hole mobility, which is mainly responsible for the relatively serious drain disturb in the programmed edge cells.

Impact of substrate bias on radiation-induced edge effects in MOSFETs

This paper investigates the effects of gamma-ray irradiation on the Shallow-Trench Isolation (STI) leakage currents in 180-nm complementary metal oxide semiconductor technology. No hump effect in the subthreshold region is observed after irradiation, which is considered to be due to the thin STI corner oxide thickness. A negative substrate bias could effectively suppress the STI leakage, but it also impairs the device characteristics. The three-dimensional simulation is introduced to understand the impact of substrate bias. Moreover, we propose a simple method for extracting the best substrate bias value, which not only eliminates the STI leakage but also has the least impact on the device characteristics.

Radiation-induced shallow trench isolation leakage in 180-nm flash memory technology

The effects of total ionizing dose (TID) irradiation on the inter-device and intra-device leakage current in a 180-nm flash memory technology are investigated. The positive oxide trapped charge in the shallow trench isolation (STI) oxide is responsible for the punch-through leakage increase and punch-through voltage decrease. Nonuniform radiation-induced oxide trapped charge distribution along the STI sidewall is introduced to analyze the radiation responses of input/output (I/O) device and high voltage (HV) device. At low dose level, the inversion near the STI corner caused by the trapped charge occurs more easily due to the lower doping concentration in this region, which gives rise to the subthreshold hump effect. With total dose level increase, more charge at deep region of the STI oxide is accumulated, predominating the intra-device off-state leakage current. It has been discussed that the STI corner scheme and substrate doping profile play important roles on influencing the device’s performance after radiation.

Total Ionizing Dose Enhanced DIBL Effect for Deep Submicron NMOSFET

Radiation enhanced drain induced barrier lowering (DIBL) effect under different bias conditions was experimentally observed and verified by 3D simulation for deep submicron MOSFETs with shallow trench isolation (STI) oxides. The off-state leakage current increased significantly after total ionizing dose (TID) above 200 krad(Si) for PASS ,OFF and ON bias condition. The irradiated devices exhibited enhanced DIBL effect, that is the off-state leakage current increases with drain voltage and DIBL parameter increases with TID. The oxide trapped charge in the STI sidewall enhances the DIBL by decreasing the drain to gate coupling, enhancing the electric field near the STI corner, and increasing the surface potential of lowly doped substrate along STI sidewall. A simple dipole theory describing the enhanced DIBL phenomenon is introduced. The phenomenon is a result of the electrostatic effect, which concentrates drain field on channel into the source along shallow trench isolation oxide. Effective non-uniform charge distribution is applied in the 3D simulation for the radiation enhanced DIBL effect. Good agreement between experiment and simulation results is demonstrated.

Ultrathin DPN STI SiON liner for 40nm low-power CMOS technology

At sub-40 nm CMOS technology nodes, the implementation of shallow trench isolation (STI) becomes more challenging due to shrinking geometries and stricter device leakage requirements. As device geometries are shrinking, STI liner is also becoming thinner and plays an important role for the minimal consumption of device active area while effectively rounding the STI corner and minimizing stress-induced defects. Consequently, STI stress is enhanced by the scaling of STI-pitch, the volume expansion induced by STI liner and film stress of filling materials. This paper discusses the benefits of SiON liner growth by decoupled-plasma-nitridation (DPN) and SiON liner induced stress compared to conventional pure oxide liner growth by in situ steam generation (ISSG). Thin STI SiON liner offers lower sub-threshold leakage current without drive current loss for transistor performance. Moreover, junction leakage current is also reduced with scaling device active area. Thus, better device performance results in better minimum operation voltage (Vcc_min) of low-power 6T-SRAM. This paper demonstrates the influences of thin STI SiON liner growth by DPN in STI manufacture.

An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors

In this paper, on-resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) degradation induced by hot-carrier injection in n-type lateral diffused metal-oxide-semiconductor transistors with shallow trench isolation (STI) in the drift region is investigated. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> unexpectedly decreases under medium- and high-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> ) stress conditions. According to experimental data and technology computer-aided-design simulation results, the mechanisms responsible for anomalous <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> shift are proposed. When the device is stressed under medium <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> , hot-hole injection and trapping occur at the STI edge closest to the channel, resulting in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> reduction. Interface trap generation (¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) occurs at the STI edge closest to the channel and nearby drift region, leading to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increase. For the device stressed under high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> reduction is also attributed to hole trapping at the STI corner closest to the channel. ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> created by hot-electron injection at the STI edge closest to the drain dominates device characteristics and leads to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increase eventually. Based on the proposed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> degradation mechanisms, an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> degradation model is discussed and verified with experimental data.

Shallow Trench Isolation Edge Effect on Random Telegraph Signal Noise and Implications for Flash Memory

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Random telegraph signal (RTS) noise is of increasing concern for sub-100-nm Flash memories. To quantitatively study the shallow trench isolation (STI) edge effect, NMOS devices with and without STI edges in the channel area are designed and analyzed. The significant impact of STI on width scaling is demonstrated and quantified. It is shown that the noise induced by STI edges dominates the RTS noise for smaller device sizes and is caused by an increase in the number of trapping sites at the STI edges. By rounding the STI corner, the number of stress-induced traps can be significantly reduced. </para>

Behavior of hot carrier generation in power SOI LDNMOS with shallow trench isolation (STI)

In this work, we investigated the hot carrier (HC) generation of power silicon-on-insulator (SOI) lateral double-diffused N-type MOSFETs (LDNMOSFET) with shallow trench isolation (STI) structure under different biasing conditions. Experimental measurements of drain and substrate currents are done. Two-dimensional (2-D) device simulation is performed to provide a better insight on the electrical behaviors of the device by looking at the electric-field (EF), electron current density ( J E) and impact ionization generation rate ( R II) distributions in the devices. The high R II site is found to be near the STI corner instead of near the channel or field oxide area close to the gate surface in standard small signal MOSFET.

Mechanism and Modeling of On-Resistance Degradation in n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors

In this study, on-resistance (Ron) degradation induced by hot-carrier injection in n-type lateral diffused metal–oxide–semiconductor transistors with shallow trench isolation (STI) in the drift region is investigated. Ron unexpectedly decreases at the beginning of stress, although Ron increases as the stress time becomes longer. Experimental data and results of technology computer-aided-design simulations reveal that hot-hole injection and trapping at the STI corner closest to the channel is responsible for the Ron reduction. The damage caused by hot-electron injection at the STI edge closest to the drain is responsible for the Ron increase. An Ron degradation model including the effect of hole trapping and interface trap generation is also discussed and verified with experimental data.

The Effect of Negative $V_{\rm TH}$ of nand Flash Memory Cells on Data Retention Characteristics

We present our study on the dependence of data retention characteristics on the threshold voltage (V TH) of the cell transistor revealing the combined effect of control gate voltage and cell transistor architecture. Data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler-Nordheim (FN) stress mainly occurs in tunnel oxide away from the region where maximum cell on-current flows. In the sub-50-nm region, due to short distance between the control gate and the shallow-trench isolation (STI) corner, the maximum cell on-current position is shifted from the STI corner to the channel center as control gate voltage decreases. The edge-thin tunnel oxide cell transistor, of which cell on-current flow is separated from tunneling current in negative cell V TH, shows 0.12-V superior data retention characteristic than the edge-thick tunnel oxide cell transistor at -3 V of cell transistor V TH in experiment.

On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region

In this letter, on-resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) degradation induced by hot-carrier injection in n-type lateral DMOS transistors with shallow-trench isolation (STI) in the drift region is investigated. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> decreases at the beginning of stress, but <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increases as the stress time is increased. Experimental data and technology computer-aided-design simulation results reveal that hot-hole injection and trapping at the STI corner closest to the channel are responsible for the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> reduction. The damage caused by hot-electron injection at the STI edge closest to the drain is responsible for the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increase.

The Effect of Trapped Charge Distributions on Data Retention Characteristics of nand Flash Memory Cells

We present this letter on the combining effect of tunnel-oxide degradation and narrow width effect on the data retention characteristics of NAND flash memory cells. Due to severe boron segregation in shallow-trench isolation (STI) corner, the cell transistor suffers from intense V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> shift on STI corner in data retention mode. Independent of enhancing the tunnel-oxide quality, the data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler-Nordheim stress mainly occurs in tunnel oxide away from STI corner. Experimental results show that V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> shift is reduced by 0.3 V or more in retention mode as the tunneling is separated from the isolation edge.

Novel cell transistor using retracted Si/sub 3/N/sub 4/-liner STI for the improvement of data retention time in gigabit density DRAM and beyond

In this paper, we propose a novel cell transistor using retracted Si/sub 3/N/sub 4/-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-/spl mu/m technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si/sub 3/N/sub 4/-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-/spl mu/m technology and beyond.

A Novel Shallow Trench Isolation with Mini-Spacer Technology

A new shallow trench isolation (STI) process with a mini-spacer at the masking nitride sidewall before silicon trench etching was proposed. With this mini-spacer, thicker corner liner oxide and a T-shaped trench oxide can be formed simultaneously. The issue of oxide-recess at STI corner can be effectively reduced and larger process window for subthreshold kink free device were obtained. The isolation capability and junction integrity were both improved as compared with those of the conventional STI process. Reverse narrow width effect as well as gate oxide integrity were also improved. This technology was employed for 0.13 µm complementary metal oxide silicon (CMOS) device fabrication.

Novel Dual Gate Oxide Process with Improved Gate Oxide Integrity Reliability

We have investigated the degradation of thick gate oxide in conventional dual gate oxide process; thick oxide grown by a new du al gate oxide process showed an improved gate oxide integrity and reliability compared with that of a conventional dual gate oxide process. To meet the requirement of integrating 3 and 6 nm dual gate oxide on a single chip operated under the bias of 1.8 and 2.5 V, respectively, this novel dual gate oxide process flow, without gate oxide thinning at a shallow trench isolation corner, was dev el- As complementary metal oxide semiconductor (CMOS) logic scales down, it needs ultrathin gate oxides and a reduced operating voltage for high performance. At the same time, however, an increas- ing number of applications require dual voltage or dual gate oxide (DGO) on a chip to interface to a higher external voltage. Moreover, to facilitate merged logic and memory circuits, DGO for memory and logic is also required. In a conventional DGO process using wet etching, a thick oxide layer is formed by reoxidizing the residual oxide after partially etching the pregrown oxide, while a thin oxide layer is grown on a clean silicon surface after thoroughly etching the pregrown oxide. Thus, the thick oxide layer in the DGO process has a tendency to poor reliability compared with a thin oxide layer and single-step-grown oxide with the same thickness. 1-4 In this paper, we describe a newly developed modified DGO (MDGO) process with higher reliability in thick oxide. By intensive study of the degradation of thick oxide through electrical and geo- metrical analyses, we report that the thick oxide is degraded due to the combined effect of severe thinning and grooving at a shallow trench isolation (STI) corner and the roughened surface of the resid- ual oxide before the second oxidation.