SHA-1 Algorithm Research Articles

FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256

Hash function algorithms are widely used to provide security services of integrity and authentication, being SHA-2 the latest set of hash algorithms standardized by the US Federal Government. The main computation block in SHA-2 algorithms is governed by a loop with high data dependence for which several implementation strategies are explored in this work as well as designs efficiently mapped to hardware architectures. Four new different hardware architectures are proposed to improve the performance of SHA-256 algorithms, reducing the critical path by reordering some operations required at each iteration of the algorithm and computing some values in advance, as possible as data dependence allows. The proposed designs were implemented and validated in the FPGA Virtex-2 XC2VP-7. The achieved results show a significant improvement on the performance of the SHA-256 algorithm compared to similar previously proposed approaches, obtaining a throughput of 909Mbps and an improved efficiency of 0.713Mbps/slice.

Compact and unified hardware architecture for SHA-1 and SHA-256 of trusted mobile computing

This paper presents a compact and unified hardware architecture implementing SHA-1 and SHA-256 algorithms that is suitable for the mobile trusted module (MTM), which should satisfy small area and l...

Alternate Approach for Implementation of SHA2 Algorithm using Feed forward Neural Network

In this paper an algorithm for one-way hash function construction based on a two layer feed forward neural network along with the piece-wise linear (pwl) chaotic map is proposed. Where SHA-2 is cryptographic hash function designed by NSA(National Security Agency). Based on chaotic neural networks, a SHA-2 Hash function is constructed, which makes use of neural networks' diffusion property and chaos' confusion property. This function encodes the plaintext of arbitrary length into the hash value of fixed length (typically, 128-bit, 256-bit or 512-bit). Theoretical analysis and experimental results show that this hash function is one-way, with high key sensitivity and plaintext sensitivity, and secure against birthday attacks or meet-in-the-middle attacks. These properties make it a suitable choice for data signature or authentication.

A hash-based image encryption algorithm

There exist several algorithms that deal with text encryption. However, there has been little research carried out to date on encrypting digital images or video files. This paper describes a novel way of encrypting digital images with password protection using 1D SHA-2 algorithm coupled with a compound forward transform. A spatial mask is generated from the frequency domain by taking advantage of the conjugate symmetry of the complex imagery part of the Fourier Transform. This mask is then XORed with the bit stream of the original image. Exclusive OR (XOR), a logical symmetric operation, that yields 0 if both binary pixels are zeros or if both are ones and 1 otherwise. This can be verified simply by modulus (pixel1, pixel2, 2). Finally, confusion is applied based on the displacement of the cipher’s pixels in accordance with a reference mask. Both security and performance aspects of the proposed method are analyzed, which prove that the method is efficient and secure from a cryptographic point of view. One of the merits of such an algorithm is to force a continuous tone payload, a steganographic term, to map onto a balanced bits distribution sequence. This bit balance is needed in certain applications, such as steganography and watermarking, since it is likely to have a balanced perceptibility effect on the cover image when embedding.

Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class

In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound analysis of hash algorithms, which is the theoretical delay limit, and Data Flow Graph transformations to achieve the iteration bound. We applied the methodology to some MD4-based hash algorithms such as SHA1, MD5 and RIPEMD-160. Since SHA1 is the algorithm which requires all the techniques we show, we also synthesized the transformed SHA1 algorithm in a 0.18 μm CMOS technology in order to verify its correctness and its achievement of high throughput. To the best of our knowledge, the proposed SHA1 architecture is the first to achieve the theoretical throughput optimum beating all previously published results. Though we demonstrate a limited number of examples, this design methodology can be applied to any other MD4-based hash algorithm.

An Empirical Analysis of Disk Sector Hashes for Data Carving

ABSTRACT Discovering known illicit material on digital storage devices is an important component of a digital forensic investigation. Using existing data carving techniques and tools, it is typically difficult to recover remaining fragments of deleted illicit files whose file system metadata and file headers have been overwritten by newer files. In such cases, a sector-based scan can be used to locate those sectors whose content matches those of sectors from known illicit files. However, brute-force sector-by-sector comparison is prohibitive in terms of time required. Techniques that compute and compare hash-based signatures of sectors in order to filter out those sectors that do not produce the same signatures as sectors from known illicit files are required for accelerating the process. This article reports the results of a case study in which the hashes for over 528 million sectors extracted from over 433,000 files of different types were analyzed. The hashes were computed using SHA1, MD5, CRC64, and CRC32 algorithms and hash collisions of sectors from JPEG and WAV files to other sectors were recorded. The analysis of the results shows that although MD5 and SHA1 produce no false-positive indications, the occurrence of false positives is relatively low for CRC32 and especially CRC64. Furthermore, the CRC-based algorithms produce considerably smaller hashes than SHA1 and MD5, thereby requiring smaller storage capacities. CRC64 provides a good compromise between number of collisions and storage capacity required for practical implementations of sector-scanning forensic tools.

The Transmission Performance Evaluation of Remote Healthcare Data over Secure Satellite Network

Objectives: We have not only examined telemedicine scenario but also applied IPSec(AH, ESP) algorithms under VPN(Virtual Private Network) for performance evaluation of telemedicine system's security and transmission. Methods: In this study, we applied IPSec(AH, ESP) algorithms under VPN(Virtual Private Network) protocol when transmit healthcare data through Satellite Network. At that time, we evaluated performance of telemedicine system through RTT(Round Trip Time), Jitter, Bandwidth that indicate to QoS(Quality Of Service). Results: It is possible to transfer remote healthcare data over Satellite Network under provided image of 15 frame and bio-signal of 10 kbps and RTT(Round Trip Time) of 774.53ms, Jitter of 25.2ms. But applying IPsec(AH, ESP) under VPN(Virtual Private Network), it is frequently happened distortion of image data affected SHA-1 and 3DES algorithm. Conclusion: In this study, it is possible to use telemedicine system for Secure Satellite Network, but demand to be based QoS(Quality Of Service) limited. We expected that it is possible to use the designed system in the disaster area.

Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs

Hash functions are common and important cryptographic primitives, which are very critical for data integrity assurance and data origin authentication security services. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. In this paper, we explore alternative architectures for the implementation of hash algorithms of the secure hash standards SHA-256 and SHA-512 on FPGAs and study their area-performance trade-offs. As several 64-bit adders are needed in SHA-512 hash value computation, new architectures proposed in this paper implement modulo-64 addition as modulo-32, modulo-16 and modulo-8 additions with a view to reduce the chip area. Hash function SHA-512 is implemented in different FPGA families of ALTERA to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to guide a designer to select the most suitable FPGA for an application. In addition, a common architecture is designed for implementing SHA-256 and SHA-512 algorithms.

Keyed/Unkeyed SHA-2

In FIPS 180–2, NIST published SHA-2 as a new version of secure hash algorithm. SHA-2 offers four secure hash algorithms including SHA-1, SHA-256, SHA-384, and SHA-512. In other words, SHA-2 may have outputs 160, 256, 384, or 512 bits of message digest. However, SHA-2 algorithm uses fixed and predefined parameters in execution. It may be vulnerable to attacks. In this paper, we propose the Keyed/Unkeyed SHA-2 for security improvement.