SEU Testing Research Articles

TID and SEU testing of the novel X-CHIP-03 monolithic pixel detector

We present a SEE and TID effect study of the novel monolithic pixel detector, X-CHIP-03, manufactured in a 180 nm SOI technology. The SEU cross section of the custom D flip-flops in the X-CHIP-03 ASIC has been evaluated using accelerated ions with LET ranging from 0.45 to 69 MeV⋅cm2⋅mg−1. The global TID response of the X-CHIP-03 has been evaluated at a dose rate of 16.2 Gy⋅min−1. The direct I-V measurements of transistor properties were made under identical radiation conditions using the predecessor X-CHIP-02 ASIC manufactured in the same technology, which contains the transistor testing matrices for TID measurements.

The orientational dependence of single event upsets and multiple-cell upsets in 65 nm dual DICE SRAM

The impact of different orientational angle of ion incidence on SEU and MCU are studied in dual DICE SRAM according to directionality of different sensitive pairs. The results show the worst orientational angle for SEU and MCU in dual DICE SRAM is incident with large tilting angle along the well even if nodal spacing of N/P sensitive pairs is the smallest. Ion tilt incidence with this orientational angle will greatly decrease SEU threshold and increase SEU cross section. At high LET, SEU saturation cross-sections in dual DICE design only has a small improvement by 40% over 6-T design whether ion incidence is normal or tilt due to charge sharing. Based on MCU topological pattern in dual DICE and 6-T design, the extent of charge diffusion and pararistic bipolar effect is quantified. Implications and application of the results for heavy ion SEU testing and RHBD technique in nanometer technology are presented.

Pattern dependence in synergistic effects of total dose on single-event upset hardness**Project supported by the National Natural Science Foundation of China (Grant No. U1532261).

The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory (SRAM) circuit. Experiments were performed under two SEU test environments: 3 MeV protons and heavy ions. Measured results show different trends. In heavy ion SEU test, the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array. TCAD simulation was performed. TID-induced degradation in nMOSFETs mainly induced the imprint effect in the SRAM cell, which is consistent with the measured results under the proton environment, but cannot explain the phenomena observed under heavy ion environment. A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.

NI Based System for Seu Testing of Memory Chips for Avionics

This paper presents the results of implementation of National Instrument based system for Single Event Upset testing of memory chips into neutron generator experimental facility, which used for SEU tests for avionics purposes. Basic SEU testing algorithm with error correction and constant errors detection is presented. The issues of radiation shielding of NI based system are discussed and solved. The examples of experimental results show the applicability of the presented system for SEU memory testing under neutrons influence.

GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs

Testing of FPGAs is gaining more and more interest because of the application of FPGA devices in many safety-critical systems. We propose GABES, a tool for the generation of test patterns for application-dependent testing of SEUs in SRAM-FPGAs, based on a genetic algorithm. Test patterns are generated and selected by the algorithm according to their fault coverage: Faults are injected in a simulated model of the circuit, the model is executed for each test pattern and the respective fault coverage is computed. We focus on SEUs in configuration bits affecting logic resources of the FPGA. This makes our fault model much more accurate than the classical stuck-at model. Results from the application of the tool to some circuits from the ITC'99 benchmarks are reported. These results suggest that this approach may be effective in the inspection of safety-critical components of control systems implemented on FPGAs.

A Versatile Link for High-Speed, Radiation Resistant Optical Transmission in LHC Upgrades

Abstract The Versatile Link project is developing a general purpose physical layer optical link with high bandwidth, radiation resistance and magnetic-field tolerance that meets the requirements of LHC upgrade experiments. This paper presents recent work on system specifications, front-end transceiver prototypes, passive components studies and commercial back-end transceiver evaluations. System optical power budgets are specified for single mode (1310nm) and multi-mode (850nm) links, with a target data rate of 4.8 Gbps and a transmission length of 150 meters. Noise and interference penalties are simulated using the 10GbE link model and verified by bit error ratio measurement on reference links. The power margin is particularly constrained by radiation degradation of the front-end receivers. We report the power budgets for all link variants where at least 1.8 dB safety margins are maintained. The Versatile Transceiver (VTRx) - the front-end module to be installed on-detector - is based on a commercial small form pluggable (SFP+) package, modified to optimize size and mass, assembled to host a qualified laser, PIN photodiode, custom-designed radiation tolerant laser driver and receiving amplifier. A set of VTRxs with validated components have been prototyped and compliance tested. We also present the radiation test results on front-end components and passive components. The total fluence tests for lasers and PINs have been carried out with pions and neutrons up to 4 x 1015/cm2. SEU tests have been performed on PIN photodiodes and the full receiver optical subassembly. Radiation induced absorption in a number of single mode and multi-mode fibers, at -25iC and up to 500 kGy, have been measured and high performance candidates identified. Commercial off-of-the-shelf parts have been examined for use as back-end transceivers. Compliance tests on SFP+, 4+4 parallel optical engines and SNAP 12 transmitter/receivers have been completed.

Effects of data rate and transistor size on single event upset cross-sections for InP-based circuits

We present results from SEU testing of two limiter-amplifier ASICs. The circuits are electrically identical except that they are fabricated using different generations InP-based HBT technology. Cross sections measured at clock speeds of 6.4 and 12.8 GHz show technology dependence, and are analyzed to determine charge collection dynamics. Our results agree with previous simulations, as well as experiments on similar technologies

Effects of beam spot size on the correlation between laser and heavy ion SEU testing

This work presents new results to compare EADS CCR laser experiments and heavy ion tests. More precisely, this study describes the influence of the laser spot size on the threshold energy of the SEU cross-section curves. A new methodology is proposed to correlate laser to heavy ion results.

A method for correcting cosine-law errors in SEU test data

Single-event upset tests often change the angle of the ion beam relative to the device to mimic a change in ion linear energy transfer, and the data are then converted via an assumed cosine law. The converted data are intended to represent device susceptibility at normal incidence, but the cosine law sometimes contains considerable error. The standard method for correcting this error is based on the rectangular parallelepiped (RPP) model. However, exact analytical expressions derived from this model are not particularly simple, so specialized computer codes are needed unless approximations are used. This paper starts with an alternate physical model, utilizing a charge-collection efficiency function, and derives an exact analytical result (called the alpha law here) that replaces the cosine law but is almost as simple as the cosine law, even when device susceptibility has a strong azimuthal dependence. The same model can be used to calculate (via numerical integrations) rates in a known heavy-ion environment. An alternative is to use model parameters to construct the parameters for an integrated RPP calculation of rates.

SEU tests performed on the digital communication system for LHC cryogenic instrumentation

The future LHC particle accelerator will use a large number of cryogenic sensors and actuators, most of which are located inside the machine tunnel and therefore in a radiation environment. These elements will communicate through a fieldbus. This paper reports the irradiation study carried out on WorldFIP fieldbus communication system. A digital communication system based on WorldFIP fieldbus protocol has been implemented and single event effects and total ionizing dose radiation tests have been performed on it.

SEU testing of a novel hardened register implemented using standard CMOS technology

A novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a standard submicron non-radiation hardened CMOS technology. This paper presents the results of heavy ion tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-section, without significant impact on the real estate, write time, or power consumption.

Charge collection and SEU from angled ion strikes

Charge collection and SEU from angled ion strikes are studied using three-dimensional simulation. The physics of charge collection in unloaded diodes and transistors is explored, as is the angular dependence of upset threshold in CMOS SRAMs. The simulation results are compared to analytical models for charge collection. Modeling fundamental transport in SRAMs, the true effective LET relationship is computed and used to analyze experimental heavy-ion data. Impacts on SEU test methodology are discussed.

Comparison of beam blanking SEM and heavy ion SEU tests on NASDA's 64 kbit SRAMs

Beam Blanking SEM (Beam Blanking Scanning Electron Microscope) was successfully used to measure and to map soft error sites on 64 kbit memory cells. Cross-section versus beam current and LET curves derived from BBSEM and heavy ion tests, respectively, have been compared. A linear relation between BBSEM current and heavy ion LET has been suggested.

Proton SEU test of MC68020, MC68882, TMS320C25 on the ARIANE5 launcher On Board Computer (OBC) and Inertial Reference System (SRI)

The ARIANE5 On Board Computer (OBC) and Inertial Reference System (SRI) are based on Motorola MC68020 processor and MC68882 coprocessor. The SRI data acquisition board also uses the DSP TMS320C25 from Texas Instruments. These devices were characterized to proton induced SEUs. But representativeness of SEU test results on processors was questioned during ARIANE5 studies. Proton test of these devices was also performed on the actual equipments with flight (or representative) software. The results show that the On Board Computer and the Inertial Reference System can satisfy the requirements of the ARIANE5 missions.

Implications of angle of incidence in SEU testing of modern circuits

Simulations show that ignoring the angular dependence of proton SEU cross sections produces errors in predictions of SEU rates in space. Moreover, they suggest that devices with thin sensitive volumes may upset to protons at grazing incidence despite high threshold LET values (>80 MeV cm/sup 2/) at normal incidence. Incorporating angular effects in space predictions requires accurate knowledge of the dimensions of the sensitive volume associated with the SEU-sensitive junction, especially the thickness. A method is proposed for using proton SEU measurements at different angles and energies combined with simulations to determine the thickness of the sensitive volume and to test the reliability of the predictions. >

Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits

Two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented. Compared to previously reported design hardened solutions, the HIT cells feature better electrical performances and consume less silicon area. SEU tests performed on a prototype chip prove the efficiency of the approach. >

Single event upsets in gallium arsenide dynamic logic

The advantages and disadvantages of using gallium arsenide (GaAs) dynamic logic in computers and digital systems are briefly discussed, especially with respect to space applications. A short introduction to the topology and operation of GaAs Two-Phase Dynamic FET Logic (TDFL) circuits is presented. Experiments for testing the SEU sensitivity of GaAs TDFL, using a laser to create charge collection events, are described. Results are used to estimate the heavy-ion, soft error rate for TDFL in a spacecraft in geosynchronous orbit, and the dependence of the SEU sensitivity on clock frequency, clock voltage, and clock phase. Analysis of the data includes a comparison between the SEU sensitivities of TDFL and the more common static form of GaAs logic, Directly Coupled FET Logic (DCFL). This is the first reported SEU testing of GaAs dynamic logic.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The single event upset environment for avionics at high latitude

Measurements of the high latitude SEU environment at avionics altitude have been made on board a commercial airliner. Results are compared with models of primary and secondary cosmic rays and atmospheric neutrons. Ground based SEU tests of static RAMs are used to predict rates in flight.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The single event upset response of the Analog Devices, ADSP2100A, digital signal processor

The authors present the results of a radiation evaluation program carried out on the ADSP2100A, which is a single-chip microprocessor optimized for 12.5 MIPS digital signal processing. Single event upset/latch-up (SEU/SEL) testing using Californium-252 was the primary aim of this program; however, accelerator heavy-ion and proton SEU/SEL data as well as total ionizing dose data are also presented. Californium-252 SEU testing covered both 12. 5- mu m and 21.3- mu m epitaxial layer DSPs, whereas only the 12.5- mu m type was tested with heavy ions and protons. Heavy-ion SEU testing covered the LET (linear energy transfer) range of 3.4 to 79.2 MeV/(mg/cm/sup 2/) and SEU testing covered the proton energies of 200, 500 and 800 MeV. A total ionizing dose rate of 64.0 rd(Si)/min was used for the cobalt-60 testing. The hardware design and software used are described and details of the various tests and test facilities are given. The authors report on the use of the SEU data for the calculation of expected in-orbit upset rates using the CREME suite of programs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

SEU simulation and testing of resistor-hardened D-latches in the SA3300 microprocessor

The SEU tolerance of the SA3300 microprocessor with feedback resistors is presented and compared to the SA3300 without feedback resistors and to the commercial version (NS32016). Upset threshold at room temperature increased from 23 MeV-cm/sup 2//mg with no feedback resistors to 60 MeV-cm/sup 2//mg and 180 MeV-cm/sup 2//mg with feedback resistors of 50 k Omega and 160 k Omega , respectively. The performance goal of 10 MHz over the full temperature range of -55 degrees C to +125 degrees C is exceeded for feedback resistors of 160 k Omega and less. Error rate calculations for this design predict that the error rate is less than once every 100 years when 50 k Omega feedback resistors are used in the D-latch design. Analysis of the SEU response using a lumped-parameter circuit simulator imply a charge collection depth of 4.5 mu m. This is much deeper than what one would expect for prompt collection in the epi and funnel regions and has been explained in terms of diffusion current in the heavily doped substrate. >