SEU testing of a novel hardened register implemented using standard CMOS technology

Abstract

A novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a standard submicron non-radiation hardened CMOS technology. This paper presents the results of heavy ion tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-section, without significant impact on the real estate, write time, or power consumption.