Settling Error Research Articles

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">including</i> on-chip reference buffers.

Robotic Endoscope System for Future Application in Minimally Invasive Laser Osteotomy: First Concept Evaluation

We are developing a robotic system for future application in minimally invasive laser osteotomy. This paper presents the mechanical system concept as a macro-milli-micro system and focuses on designing and evaluating the milli-system. The milli-system consists of an articulated tendon-driven robotic endoscope with seven rigid links with an outer diameter of 8mm connected by six discrete rotational joints (±30°). These joints can be controlled individually, however, controlling one joint’s motion influences all joints located more distally, making joint control an interesting challenge. Controlling each joint as desired will allow positioning the micro-system mounted at the endoscope’s tip. The micro-system is itself a robot that will accurately position the laser. The robotic endoscope incorporates a hollow core with a diameter of 4.8mm that holds a supply channel for the micro-system with the necessary means for actuation and surgical intervention. We demonstrated the functionality of the robotic endoscope in tracking experiments. Despite the joints’ mutual influence, the articulated robotic endoscope could be handled successfully and achieved an angular settling error of less than 1° in the individual joints. The overall robotic system’s functionality was successfully demonstrated with a time-synchronized joint movement of the macro-system (serial manipulator) and the robotic endoscope.

A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS

This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the least significant bits (LSBs) in the digital-to-analog capacitor array, which reduces the incomplete settling error and releases the requirements on the RV-buffer to achieve lower power dissipation. The SAR ADC is fabricated in 40-nm CMOS technology occupying 0.13 mm $$^{2}$$ area. At 1.1 V supply voltage and 80 MHz sampling frequency, the ADC achieves 50.7 dB SNDR, 69.5 dBc SFDR with a 1 MHz input at −8 dBFS. The total power consumption of the ADC is 2.99 mW, including the reference buffer power consumption of 2 mW. The Schreier FoM is 164.1 dB.

Slewing Mitigation Technique for Switched Capacitor Circuits

Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power.

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1 mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.

An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS

This brief presents an 8-bit 350-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with 1.5 b/cycle redundancy in 65-nm CMOS. With 12.5% redundancy in conversion cycles, conversion errors caused by capacitor mismatch, offset and DAC settling errors can be addressed. Compared to the conventional 1.5 b/cycle operation, the proposed switching removes the pre-set phase and thus reduces the speed and power penalty. Besides, with this switching scheme, only two reference voltages are needed instead of five in the conventional scheme. The prototype achieves 45.7 dB SNDR at Nyquist input and consumes 2.1 mW from a 1.2 V supply, resulting in a Walden FoM of 38.1 fJ/conversion-step.

Proportional-integral-derivative controller parameter optimisation based on improved glowworm swarm optimisation algorithm

The proportional-integral-derivative (PID) controller parameters tuning, is seeking the optimal value in the space of three parameters to achieve the optimal control performance of the system. It is the core of contemporary feedback control system design. However, its easily falling into local optimum weakened its global search ability. To tackle this problem, this paper proposes an improved glowworm swarm optimisation algorithm, (D-AGSO) with the introduction of directed moving and adaptive step strategy. The simulation experimental results show that D-AGSO continuously adapts the tuning parameters, achieving lower fluctuations features, time settling and smaller steady state error, specially applied to the time delay in the case of inertia controlled system of industrial production.

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits

To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over $3\times $ improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA’s process scalability by comparing the measured results of the DA-based MDAC prototyped in 65- and 28-nm CMOS. We observe $2\times - 3\times $ improvement in speed, power, and area mainly resulting from the DA’s process scalability.

A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique

A performance-boosting frequency-compensation technique, called feed-forward Gm-stage and regular Miller plus indirect compensation (FGRMIC), is presented in this paper. The proposed structure consists of three parts that ensure the stability and significantly improve the performance, such as gain–bandwidth product (GBW), slew rate, and sensitivity. The first part is a feed-forward transconductance stage, and the second part is a Miller capacitor in series with one resistor. The third part is an indirect compensation capacitor combined with a resistor. Detailed theoretical analysis and design considerations are provided to demonstrate the stability of the compensation scheme. Measurement results show that the implemented amplifier, driving a 2-pF load capacitance, achieves a GBW of 2.41 GHz with a phase margin of 82.6° while consuming 12.6 mW with a 1.2-V supply voltage in a TSMC 65-nm CMOS technology. Large-signal step response indicates that the implemented three-stage FGRMIC amplifier settles with 1% settling error within 1.41 ns.

A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current

Pipeline analog-to-digital converters (ADCs), which dominated high-speed and high-resolution applications, suffered from weak improvement in power efficiency. To address such a problem, this brief presents a 14-bit split-pipeline opamp-sharing ADC, with background calibration that optimizes duty-cycle ratio and amplifier power consumption in the shared opamp. Based on the interstage gain (that includes settling) error estimated by the split ADC calibration engine, the clock duty-cycle ratio and the bias current are adjusted to achieve better dynamic settling and resolution trade-offs. Operating at 100 MS/s with a 9-MHz input signal, the ADC achieves 46.5 dB of signal-to-noise-and-distortion ratio (SNDR) and 59.6 dB of spurious-free dynamic range (SFDR) before calibration, and after calibration, it improves to 71.7 dB of SNDR and 84.4 dB of SFDR, respectively. The ADC maintains an SNDR over 68.5 dB within the full Nyquist bandwidth consuming 32 mW of power, which yields a Walden figure-of-merit (FoM) of 147.2 fJ/conversion-step and a Schreier FoM of 160.4 dB.

Optimal dynamic range scaling of ΔΣ ADC using bias current estimation

In this paper, optimal dynamic range scaling of ΔΣ ADC using bias current estimation method is proposed. Generally, a different dynamic range scaling gives different feedback factor and effective load capacitance to each integrator in the ΔΣ ADC. It means that power consumption of each integrator strongly depends on the coefficient of the integrator. Therefore, the proposed method estimates which dynamic range scaling consumes the least power to achieve a given settling error. To verify the effectiveness of the proposed method, the noise coupled third order ΔΣ ADC having different dynamic scaling with transistor level opamps was simulated to compare the ADC performance.

A 24- $\mu \text{W}$ 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS

This paper presents an energy-efficient 12-bit successive approximation (SA) register analog-to-digital converter (ADC) for high-performance sensor systems. The ADC uses a two-step decision digital-to-analog converter (DAC) switching scheme for improving the DAC linearity with small capacitor arrays. The scheme effectively eliminates the largest binary DAC middle-code transition glitch. The proposed switching scheme also tolerates DAC settling errors during SA. Avoiding unnecessary DAC switching error improves the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR). A reference-scaling binary capacitor DAC is used for improving the ADC energy efficiency without sacrificing production reliability. The implemented prototype in 0.11- $\mu \text{m}$ CMOS occupies an active area of 0.097 mm2. At 1 MS/s, it consumes a total power of 24 $\mu \text{W}$ from a 0.9 V supply. The measured differential nonlinearity and the integral nonlinearity are 0.4 least significant bit (LSB) and 0.7 LSB, respectively. Among 50 chips, the peak measured SNDR is 68.3 dB. The peak and the average of SFDR are 89 and 83.5 dB, respectively. The optimal effective number of bits is 11 bit at the Nyquist-rate input, which is equivalent to a figure of merit of 11.7 fJ/conversion-step.

A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC

This paper presents an opamp-free solution to implement noise shaping in a successive approximation register analog-to-digital convertor. The comparator noise, incomplete settling error of digital-to-analog convertor and mismatch are alleviated. Designed in a 65 nm CMOS technology, the prototype realizes 58 dB SNDR at 50 MS/s sampling frequency. It consumes 120.7 μW from a 0.8 V supply and achieves a FoM of 14.8 fJ per conversion step.

SETTLING TIME MINIMIZATION OF THREE-STAGE CROSSED FEEDFORWARD REVERSED NESTED-MILLER AMPLIFIER

Conventional frequency response compensation methods for three-stage amplifier are not appropriate for fast transient response viewpoint. Therefore, herein, we have utilized the minimum settling time (MST) approach to compensate the crossed feed-forward reversed nested Miller compensation (CFRNMC) amplifier which was previously compensated by the conventional frequency response methods. Compensation rules for the considered amplifier are proposed based on time-domain parameters. The three-stage amplifier is designed in a 90 nm CMOS technology with the power supply of 1 V. The amplifier drives the capacitor load of 100 pF and its closed-loop time response to a unit-step input has a settling time less than 34 ns with 1% settling error.

A Digitally Corrected 5-mW 2-MS/s SC $\Delta\Sigma$ ADC in 0.25-$\mu$m CMOS With 94-dB SFDR

A digital correction scheme that allows a switched-capacitor (SC) ΔΣ ADC to operate with significantly reduced power consumption is proposed. As power dissipation is reduced in the integrators, nonlinear settling errors cause increasing harmonic distortion. The correction technique uses a polynomial approximation to correct the nonlinearity and reduce distortion in the post-filtered digital output. With correction, experimental results yield a peak SNDR of 75 dB, a THD of -90 dB and a SFDR of 94 dB. The total analog power dissipation of the corrected modulator is 5 mW at 2.4 V, saving 38% over a similarly performing uncorrected modulator output. The active area is 0.39 mm2 in 0.25-μ m CMOS.

Relationship between settling time and pole–zero placements for three-stage CMOS opamp

In this article, the effect of pole–zero placements on settling time has been analysed for a three-stage CMOS operational amplifier (opamp) with nested Miller compensation (NMC) and reversed nested Miller compensation (RNMC) schemes. In this study, optimised balancing of speed and power is done for a three-stage CMOS opamp for a given load condition (on-chip opamp). Optimum values of circuit parameters have been derived for power efficient shifting of poles and zeros. The effect of placement of poles and zeros on dynamic settling error (DSE) is analysed by means of numerical simulation using MATLAB. This analysis will be useful to ascertain the relationship between pole–zero placements and settling time. The study of the effects of compensation elements on pole–zero placements has been done to assist the circuit designers to achieve better performance. Analysis of the effect of capacitive load on pole–zero placements and DSE has been done in this study. A technique has been developed to find out the upper and lower limits of compensation capacitor that allows fast settling with low power. The validity of the analytical work has been checked by simulation using Tanner tool in 0.35-µm CMOS technology. In the case of RNMC scheme, a power dissipation of 60.17 µw and a settling time of 340 ns are achieved; the results obtained are better than the earlier reported design technique. In the case of NMC, the simulation has been done to validate the analytical analysis.

An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.

Switched-current signal processing for video frequencies and beyond

Switched-current (SI) signal processing circuits with video frequency performance are presented. The delay cells employ negative feedback to produce a 'virtual earth' at the input node to improve transmission accuracy. Fully differential structures with common-mode feedback are used to reduce charge injection errors and crosstalk from digital signals. An IC test circuit, in a 1 mu m standard digital CMOS process, containing simple delay lines and an FIR filter section is described, and measured performance is given. Typically, a 2T delay line sampling at 13.3 MHz gave a low-frequency gain error of -54 dB, a settling error of -60 dB, a third-harmonic distortion of -40 dB with 75% modulation, and an S/N ratio of 60 dB. Scaling of the memory cell device dimensions and currents should permit SI operation at clock frequencies beyond 100 MHz. >