Abstract
Switched-current (SI) signal processing circuits with video frequency performance are presented. The delay cells employ negative feedback to produce a 'virtual earth' at the input node to improve transmission accuracy. Fully differential structures with common-mode feedback are used to reduce charge injection errors and crosstalk from digital signals. An IC test circuit, in a 1 mu m standard digital CMOS process, containing simple delay lines and an FIR filter section is described, and measured performance is given. Typically, a 2T delay line sampling at 13.3 MHz gave a low-frequency gain error of -54 dB, a settling error of -60 dB, a third-harmonic distortion of -40 dB with 75% modulation, and an S/N ratio of 60 dB. Scaling of the memory cell device dimensions and currents should permit SI operation at clock frequencies beyond 100 MHz. >
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