Serial Adder Research Articles

Design of Reversible Serial Adder Based on EPOE Expressions for Computational Applications

Considering the growing trend toward reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers. One of the solutions to reduce power consumption is the design of reversible circuits. This paper proposed the design of a low-cost self-control serial adder system. In the proposed circuit, EPOE expressions have been used for the direct and compact design of sequential circuits to reduce the fixed inputs of sequential logic circuits. In addition, to reduce the quantum cost, common terms between the outputs are optimally used. Also, limiting the use of Tofoli gates with a size larger than three inputs in the implementation of the final circuit will reduce the quantum cost of the resulting circuit. The results and comparisons showed that the proposed design has improved efficiency measures including quantum cost, garbage outputs, and fixed inputs compared to existing works.

Quantum-based serial-parallel multiplier circuit using an efficient nano-scale serial adder

Quantum-based serial-parallel multiplier circuit using an efficient nano-scale serial adder

High-Speed Serial–Parallel Multiplier in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a nanotechnology-based circuit design technology to design efficient circuits. Serial–parallel multiplier (SPM) is an efficient hardware circuit used in different applications ranging from simple arithmetic circuits, filters to complex cryptographic systems. In this work, an architecture that can be used for realizing SPM in QCA is discussed. Based on that architecture, an efficient 4-bit SPM is implemented in QCA. The proposed multiplier is also realized using efficient shift registers and adders. Parallel and serial shift registers are introduced in the circuit to store the inputs and outputs to increase the reliability of the circuit. The proposed work is the first of its kind to implement SPM with shift registers to store input and output in QCA. The proposed multiplier without shift registers is efficient and at least 66% faster compared to existing designs. The 4-bit multiplier with shift registers has 2271 cells covering an area of 7.74 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}} ^{2}$ </tex-math></inline-formula> with 25.25 clock cycle latency. To showcase, the scalability of a serial adder is also realized using the universal, scalable, and efficient clocking scheme.

Recurrent neural network from adder’s perspective: Carry-lookahead RNN

The recurrent network architecture is a widely used model in sequence modeling, but its serial dependency hinders the computation parallelization, which makes the operation inefficient. The same problem was encountered in serial adder at the early stage of digital electronics. In this paper, we discuss the similarities between recurrent neural network (RNN) and serial adder. Inspired by carry-lookahead adder, we introduce carry-lookahead module to RNN, which makes it possible for RNN to run in parallel. Then, we design the method of parallel RNN computation, and finally Carry-lookahead RNN (CL-RNN) is proposed. CL-RNN takes advantages in parallelism and flexible receptive field. Through a comprehensive set of tests, we verify that CL-RNN can perform better than existing typical RNNs in sequence modeling tasks which are specially designed for RNNs. Code and models are available at: https://github.com/WinnieJiangHW/Carry-lookahead_RNN.

Efficient designs of reversible sequential circuits

Recently, the synthesis of reversible sequential circuits has attracted researchers’ attention for implementing low-power logic designs. So far, the direct and replacement techniques have been used in the reversible sequential circuits design. The replacement technique leads to high quantum cost. There is the principle to look for efficient reversible circuits composed of Clifford + T gates by optimizing quantum cost, the number of T gates, and particularly the T-depth of the circuit, which depends on the type and layout of the reversible gates used in the function. This paper has proposed an optimized version of direct feedback technique without any flip-flops and is performed on several samples of reversible circuits design, such as counters and shift registers. It has been shown that by partial changes in the direct technique, quantum cost and other cost metrics have been improved. It has also displayed some efficient designs of the reversible parallel-to-serial converter with parity capability and low-cost design of the control unit for a reversible self-controlled serial adder system. The analysis and comparison depict that all new proposed designs have optimized the existing works in terms of performance variables, including quantum cost, number of T gates, and T-depth of the circuit.

VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH

In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard &amp; fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.

Stacked Blumlein Pulsers With Distributed Adders

The development of the Fitch and Howell approach to the powerful rectangular nanosecond pulses formation by the summation of partial pulses generated by a set of double forming lines is considered in this article. Generators designed according to this scheme are often used in pulse power applications and are usually called stacked Blumlein pulser. A variant of a transition from the Fitch circuit using a lumped partial pulses adder to a circuit using a distributed serial adder is shown. The designs of pulse generators with distributed serial adders are shown. The conditions for matched summation of partial pulses in a distributed serial adder are formulated. The results of simulating the operation of the generators in the matched and unmatched modes of summing partial pulses are presented. Formulas for the calculation of shape parameters of pulses in matched and unmatched modes are given (rise time, fall time, amplitude).

Design of QCA-Serial Parallel Multiplier (QSPM) With Energy Dissipation Analysis

This brief presents an efficient single-layer serial-parallel multiplier (SPM) in Quantum-dot Cellular Automata (QCA). We have designed a bit-serial adder (BSA) using a fully utilized majority gate (MV), and a modified E-shaped exclusive-OR (E-XOR) gate. The cell-interactive properties of the QCA cell have been utilized to realize the proposed E-XOR gate. This new gate leads the proposed SPM to achieve a reduction in cell count and area by 30% and 19%, 29% and 24%, 30% and 22%, 32% and 39%, and 36% and 46% for 4-, 8-, 16-, 32-, and 64-bit multipliers, respectively. All proposed circuits have been simulated and verified by using QCADesigner with a coherence vector simulation engine. In addition, the average switching and leakage energy dissipation are estimated using QCAPro tool.

Low-cost and compact design method for reversible sequential circuits

Reversible logic plays an important role in nanotechnology-based systems; therefore, it has become an interesting topic for many researchers in this field. Although many researchers are investigating techniques to synthesize reversible combinational logic, few are working in the field of reversible sequential logic. The traditional method to design a sequential circuit is a replacement technique. In this technique, in order to design a reversible sequential circuit, all parts of an irreversible design (e.g., latches and flip-flops and associated combinational gates) are replaced by their reversible counter parts, which leads to circuits with high quantum cost. In this paper, we propose a direct and compact design of reversible synchronous sequential circuits. The EXOR of Products of EXOR (EPOE) expressions are applied, to reduce the quantum cost of sequential logic circuits. We present designs for some practical sequential circuits, such as state machines, counters and shift registers. To show the efficiency of the proposed method, we have designed a proof of concept of our designs to design a practical sequential system: a reversible self-controlled serial adder. Our designs considerably reduce performance cost factors: including quantum cost, number of constant inputs or the number of garbage outputs and delay.

A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application

Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[Formula: see text]V at 6.6[Formula: see text]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.

Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays

Low operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid CMOS nano-crossbar arrays. In-memory serial adders have been theoretically and experimentally proven for crossbar arrays. To harness the parallelism of memristive arrays, parallel-prefix adders can be effective. In this work, a novel mapping scheme for in-memory Kogge-Stone adder has been presented. The number of cycles increases logarithmically with the bit width N of the operands, i.e., O ( log 2 N ), and the device count is 5 N . We verify the correctness of the proposed scheme by means of TaO × device model-based memristive simulations. We compare the proposed scheme with other proposed schemes in terms of number of cycle and number of devices.

Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement

Ultra-low-voltage (ULV) satisfies the energy-constraint on-die acceleration of parallel processing in battery-powered Internet-of-Things applications. However, ULV brings serious leakage energy, throughput reduction, and delay variation issues. Parallel bit-serialization remarkably reduces leakage energy and enhances area efficiency; however, extremely reduced critical path aggravates delay variation makes bit-serial operation not feasible to ULV design. In this paper, we propose a balanced-bit-serial adder (BBSA) as a basic unit of parallel-balanced-bit-serialization (PBBS) operation, which leverages timing borrowing to mitigate delay variation. In addition, we propose two latches to improve the effectiveness of timing borrowing and ease the area and power overhead of BBSA. The proposed BBSA is verified in TSMC 40-nm CMOS technology. Compared with the flip-flop-based bit-serial adder, energy consumption of BBSA is saved by 40% and area efficiency is improved by 15% as well. As a practical demonstration, we present a reconfigurable PBBS single instruction multiple data (SIMD) vector processing tile. The post-layout simulation shows that the proposed design has advantage of overall area efficiency and has significant energy saving as compared with the state-of-art ULV SIMD tile.

SERIAL ADDER BASED MULTIPLICATION AND ACCUMULATION UNIT (MAC)

For efficient digital FIR filter applications, the Multiplication and Accumulation (MAC) unit is implemented by using various methods. In a digital filter, the MAC unit is one of the main units for performing multiplications and additions. This paper presents an efficient filter design for digital signal processing (DSP) applications with the reduction of carry propagation. In general, the performance of transpose filter mainly depends on the design of MAC unit. The design of a traditional filter consists of a large number of logical elements and has a high computational delay due to the conventional MAC unit. To design an efficient MAC unit, a serial adder is employed by using 2:1 multiplexer and a shifter block. The proposed work is implemented by using Xilinx ISE synthesis tool.

Novel Optimized Designs for QCA Serial Adders

Novel Optimized Designs for QCA Serial Adders

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

Performance Evaluation of Sequential Adder using Neural Networks

Objectives: Power consumption in digital systems is a crucial issue with the greater emphasis on nano-scaled technologies. Power consumption is greatly curbed by reducing the voltage levels. However, this compromises the circuit delay. Also, by decreasing the voltage level, circuit delay rises exponentially and hence there is an increase in static energy consumption. Methods/Statistical Analysis: In this paper, adders are the architectures chosen for optimization due to the fact that in most of the modern digital systems, the maximum operating speed depends on how fast adders can process the data. This, in turn, is responsible for setting the minimum clock cycle time in processors. The primary focus of this paper is to reduce the delay of Serial Full Adder (SFA), a sequential adder. The delay, power, and area of six different 16-bit adders are examined and compared with respect to their structure and logic depth. This paper presents optimized architectures for 32-bit and 64-bit SFA which operates with less delay and occupies less area by using massively parallel structures. Introducing the concept of neural networks helps us to formulate a power estimation method for adder architectures in SOC Using supervised learning method in Feed Forward Back Propagation Network, the estimated dynamic, leakage and total power is obtained for SFA for any desired input voltage. Findings: The experimental results shows that proposed SFA provides better results with power and delay as metric. The convergence of the proposed estimation method based on neural networks is faster due to its learning and training. Application/Improvements: This method can be extended to estimate the power of any adder architecture and using any other neural network.

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

SummaryQuantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley &amp; Sons, Ltd.

An efficient ternary serial adder based on carbon nanotube FETs

This paper presents an efficient ternary serial adder for nanotechnology employing negative, positive and standard ternary logics. Multiple-valued logic results in chips with more density, less complexity and high-bandwidth data transfer. The unique properties of CNTFETs such as the capability of adapting the desired threshold voltage by changing the diameters of the nanotubes and same carrier mobility for the n-type and p-type devices play an important role in designing this circuit. The proposed design method considerably reduces the number of required devices of a ternary serial adder. In addition, the results of the simulations conducted using HSPICE with the Stanford comprehensive 32 nm CNTFET model, demonstrate improvements in terms of speed and power-delay product as compared to the cutting-edge CNTFET-based ternary designs.

Molecular Logic Computation with Debugging Method

Seesaw gate concept, which is based on a reversible DNA strand branch process, has been found to have the potential to be used in the construction of various computing devices. In this study, we consider constructing full adder and serial binary adder, using the new concept of seesaw gate. Our simulation of the full adder preformed properly as designed; however unexpected exception is noted in the simulation of the serial binary adder. To identify and address the exception, we propose a new method for debugging the molecular circuit. The main idea for this method is to add fan‐outs to monitor the circuit in a reverse stepwise manner. These fan‐outs are fluorescent signals that can obtain the real‐time concentration of the target molecule. By analyzing the monitoring result, the exception can be identified and located. In this paper, examples of XOR and serial binary adder circuits are described to prove the practicability and validity of the molecular circuit debugging method.