Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays

Abstract

Low operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid CMOS nano-crossbar arrays. In-memory serial adders have been theoretically and experimentally proven for crossbar arrays. To harness the parallelism of memristive arrays, parallel-prefix adders can be effective. In this work, a novel mapping scheme for in-memory Kogge-Stone adder has been presented. The number of cycles increases logarithmically with the bit width N of the operands, i.e., O ( log 2 N ), and the device count is 5 N . We verify the correctness of the proposed scheme by means of TaO × device model-based memristive simulations. We compare the proposed scheme with other proposed schemes in terms of number of cycle and number of devices.