Abstract
For efficient digital FIR filter applications, the Multiplication and Accumulation (MAC) unit is implemented by using various methods. In a digital filter, the MAC unit is one of the main units for performing multiplications and additions. This paper presents an efficient filter design for digital signal processing (DSP) applications with the reduction of carry propagation. In general, the performance of transpose filter mainly depends on the design of MAC unit. The design of a traditional filter consists of a large number of logical elements and has a high computational delay due to the conventional MAC unit. To design an efficient MAC unit, a serial adder is employed by using 2:1 multiplexer and a shifter block. The proposed work is implemented by using Xilinx ISE synthesis tool.
Highlights
Tri-state logic based Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter implementation are discussed in [1]
The following sections give the overview of FIR design with serial adder and their performance in terms of number of slices, Look Up Table (LUT), and delay
The proposed serial adder is implemented by using Verilog Hardware Description Language (HDL).The simulation results are evaluated by using Modelsim XE and the synthesis is estimated by using the Xilinx ISE software
Summary
Tri-state logic based Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter implementation are discussed in [1]. A simple first order filter with multiple outputs is designed in [2] which require only four adders and a delay and multiplier unit. A non-recursive digital filter is designed in [4] using fixed point binary coefficient The complexity of such a design depends on the number of adders used in the multiplier section. The complexity of standard binary representation is reduced by using Canonic Signed Digit (CSD) representation It requires fewer adders than Bull and Horrocks algorithm. A hardware optimization is discussed in [5] using CSD representation It determines the minimum order filter at first by assuming that the filter coefficients are infinite precision. An approach to reduce the complexity of parallel FIR filter is discussed in [7] It uses linear and iterated short convolution techniques. The following sections give the overview of FIR design with serial adder and their performance in terms of number of slices, Look Up Table (LUT), and delay
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