Abstract
The most widely used operation in digital signal processing is Multiply and Accumulate (MAC) unit. The area occupied by the MAC unit and the power consumed will largely affect the performance and speed of the electronic system. So in this paper we have proposed a 32-bit MAC using 32-bit array multiplier and RCA (ripple carry adder) along with another MAC using vedic multiplier and RCA. The paper also has another modified MAC unit which uses vedic multiplier and carry save adder. All the MAC units are simulated using ModelSim software and synthesis is done using XILINX ISE DESIGN SUITE. All the MAC implementations were compared with each other for the area and delay. The proposed design of MAC using vedic multiplier has less delay with respect to other MAC architectures.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
