Serial Adder Research Articles

Realisation of morphological operations

Multi-input min and max operators are two essential components for dilation and erosion, which are two basic building units for morphological filtering. Many of the more complicated operations of morphological filtering can be decomposed by them. The min or max operator cascades after a bit-serial adder or subtractor is equal to a dilation or erosion operator. In the paper, an efficient algorithm and its implementation architecture for the min/max operation are proposed. The proposed algorithm and architecture can process bit by bit directly for all input signals without using threshold decomposition which requires more complicated hardware design. Any shape and size of the filtering window or structuring element can be realised. For a fixed window size, the shape of window is programmable by changing some input initial conditions. The computation time is independent of, and the hardware complexity is linear to, the window size. This implies that a very high throughput rate can be attained after an initial latency period required to fill up the pipeline. The proposed architecture is modular, regular and of local interconnections; and therefore amenable for VLSI implementation.

Bit-serial multipliers and squarers

Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries. >

Design of a square-root architecture: digit-serial approach

Abstract A new digit-serial square-root architecture based on radix-2n arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of/i-bit controlled add/subtract (CAS) cells. We present two CAS cell architectures. The first is based on the conventional carry feed-back digit serial adder. The second is based on the carry feed-forward adder structure which results in the first reported square-root architecture that can be pipelined down to the bit-level. Furthermore, there is no specification of the type of adder used in the CAS cell. It can be a carry look-ahead or a carry propagate adder. The proposed architecture is general for any digit size and any wordlength.

Overflow detection in multioperand addition

An algorithm is developed to detect overflow in multioperand addition. The algorithm is extended to support generic commercial arithmetic adder chips. This algorithm is used in conjunction with a multioperand carry-save adder and a multioperand bit-serial adder to detect overflow. Provision is also made in these circuits to incorporate subtraction of operands. CAD tools are used to simulate the logic in hardware for the verification of the algorithm.

High-performance bit-serial adders and multipliers

A design methodology is presented which uses clocked logic modules to synthesise flexible high performance multipliers. By using two-stage pipelined bit-serial adders, a bit-serial multiplier can be designed which is capable of producing both single- and double-precision products for continuous two's complement data streams. High processing speeds are possible owing to the systolic structure which is pipelined at the gate level.

A case for digit serial VLSI signal processors

Digit serial architectures, which have digit serial data transmission combined with digit serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit serial input are overcome if the input is overlapped with the computation--what we refer to as digit pipelining. Digit pipelining allows us to break up long strings of combinatorial logic and, thus, to increase the clock rate of the system while still preserving much of the circuit structure. In general, for a modest increase in hardware (which in VLSI translates to a modest increase in area) digit serial architectures offer the potential of higher throughput than equivalent word parallel architectures. Several designs for various digit serial adders are presented. Then two filter examples are discussed that use the digit serial adders to achieve digit pipelining.

Novel dynamic CMOS logic free from problems of charge sharing and clock skew

A novel four-phase dynamic CMOS logic is proposed, analysed and chip-tested. There are two circuit configurations in the new dynamic logic. One of these can completely get rid of the problems of charge sharing and clock skew, which are inherent in most of the dynamic circuits. The other, although it can only prevent the charge sharing problem, has a larger tolerance of the clock skew than the conventional four-phase precharge-discharge logic. The second configuration is more flexible in logic design than the first configuration. Both configurations use only three clock phases to form the four-phase dynamic circuits. After a brief analysis of the clock skew problem of the conventional four-phase logic, the new dynamic logic is introduced and the two circuit configurations are described. Then, the basic analysis on the device size design and performance evaluations of the new logic are given. A serial full adder was designed and implemented by a 3.5 /jm p-well CMOS process and the experimental results obtai...

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VLSI design has caused a revolution in microminiaturization. The design process requires construction of stick diagrams for the digital circuit to be designed. These diagrams are prepared using different colored layers. The color graphics and the color monitors make the overall system quite expensive. The object of this article is to show how an inexpensive personal computer like the Apple MacIntosh can be used for preparing VLSI stick diagrams. The Apple MacIntosh's capabilities include translation, mirroring, detail work and hatching; which are indispensible in the construction of stick diagrams. The stick diagrams for a few examples such as serial adder, half adder, adder/subtractor and generalized pipeline array cell have been worked out. It is hoped that this paper will aid in making VLSI design easier on less expensive and easily obtainable personal computers.

VLSI design using Apple MacIntosh

VLSI design has caused a revolution in microminiaturization. The design process requires construction of stick diagrams for the digital circuit to be designed. These diagrams are prepared using different colored layers. The color graphics and the color monitors make the overall system quite expensive. The object of this article is to show how an inexpensive personal computer like the Apple MacIntosh can be used for preparing VLSI stick diagrams. The Apple MacIntosh's capabilities include translation, mirroring, detail work and hatching; which are indispensible in the construction of stick diagrams. The stick diagrams for a few examples such as serial adder, half adder, adder/subtractor and generalized pipeline array cell have been worked out. It is hoped that this paper will aid in making VLSI design easier on less expensive and easily obtainable personal computers.

Comments on "Inner Product Computers"

The results for different hardware configurations of inner product computers presented by Swartzlander et al.1 are in error. In their Table I, the pipelined quasi-serial processor is credited with the ability to evaluate a complete inner product in 10 ns. The clock rate may be 10 ns but several clocks are required to evaluate one inner product. (Note the serial adder feeding the result register in their Fig. 2.)

Serial Adders with Overflow Correction

A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.

The Serial Adder as a Universal Decision Element

Mathematical Logic QuarterlyVolume 16, Issue 6 p. 319-320 Article The Serial Adder as a Universal Decision Element K. H. E. Whittle, K. H. E. Whittle Boston and Nottingham (England)Search for more papers by this author K. H. E. Whittle, K. H. E. Whittle Boston and Nottingham (England)Search for more papers by this author First published: 1970 https://doi.org/10.1002/malq.19700160603AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat No abstract is available for this article. Volume16, Issue61970Pages 319-320 RelatedInformation

Serial adder for bits occurring in reverse time sequence

A serial adder is described which enables individual bits to be added serially into an accumulating register as they are formed, despite the fact that they appear in the reverse order to that normally required.

High-speed serial binary adder

High-speed serial binary adder

Some New High-Speed Tunnel-Diode Logic Circuits

Several high-speed tunnel-diode logic circuits are presented which perform majority-type logic or majority-type logic with inversion, and make use of a multiphase sinusoidal power supply to obtain signal directivity. Laboratory results are presented which show operation of these circuits at a 125 Mc/sec pulse repetition rate with 2 nsec delay per logical decision. The circuits have also been operated at 250 Mc/sec. A comparison which is made between these circuits and some of the tunnel-diode logic circuits previously reported in the literature reveals certain system advantages of the new circuits. Preliminary results of both analog and digital computer analyses of the systems of nonlinear differential equations which describe these circuits are presented. These results have been in excellent agreement with those found in the laboratory. A full serial binary adder is described which produces a carry output in 2 nsec and the sum output in 4 nsec.

A directly-coupled serial adder designed for use in a digital differential analyser

A brief introduction to the technique of directly-coupled logical circuits is given together with basic logical circuit diagrams. It is proposed that for maximum economy and optimum operational reliability, a single type of transistor and a single value of resistor should be used throughout the equipment and that design reliability should be based on the probability of worst-case parameters not being exceeded. Practical designs based on the above theories are shown and limited reliability figures quoted.

All-Magnetic Logic Elements Using Strained Permalloy Wire

An element for performing digital logic which employs Permalloy wire, solenoids, and resistors and utilizes a two-phase current pulse source has been studied experimentally. The reentrant hysteresis loop exhibited by a torsionally strained Permalloy wire provides the mechanism for power gain. A balanced input circuit assures unidirectional information flow and provides means for obtaining logic functions. Each element consists of two 0.6-in. bifilar-wound solenoids for bias and reset pulse currents, one or several 0.025-in. solenoids to which logic inputs are applied, an output resistor and a Permalloy wire core. The application of a bias current pulse to the logic element will cause the magnetization to change from the zero to the one state provided a signal is present simultaneously at the input to nucleate the magnetization reversal. The reset current pulse switches the magnetization back again and produces an output across the bias coil which is used to control one or several following elements. A buffer zone, the magnetization of which is controlled by the reset pulse, separates adjacent logic elements to minimize element interaction. Measurements on elements employing a 1.5-mil, 5–79 Permalloy core show that a switching time of 15 μsec and a power gain of 10 can be achieved. Preliminary tests indicate satisfactory operation over the temperature range of −55° to +185°C. These elements have been used to construct flip-flops, binary counters and a serial adder which employs majority logic. The circuits operated successfully when the pulse currents from the power supply were varied by ±20%. Because an open flux structure is used, it is believed that similar techniques will have application in circuits employing deposited magnetic films.

A Transistor Shift Register and Serial Adder

A small set of basic functions, such as binary memory and elementary binary logic, can be remarkably versatile; such functions are important in switching and computing. This paper describes a piece of computing equipment which can store a pair of binary numbers and add them, producing the sum a digit at a time. The equipment is built from a basic set of functional blocks, all of which are designed around transistors. This set of building blocks consists of a binary cell, a pulse amplifier, a pulse amplifier with delay, and logic circuits. The binary cell is a flip-flop; amplifiers are monostable circuits, and logic is performed in diode gates. Some interesting special features arise from the use of transistors. These features are discussed and the designs are evaluated.