Sequential Lateral Solidification Research Articles

Room-temperature crystallization of amorphous silicon by near-UV femtosecond pulses

Near ultraviolet (λ ≈ 400 nm) femtosecond laser annealing (400 nm-FLA) in a scanning mode was employed to crystallize amorphous silicon (a-Si) films at room temperature. The average grain size of polycrystalline silicon annealed was studied as a function of the incident laser fluence and beam overlap or the number of laser shots irradiated. In general, the grain size can be enlarged by either increasing the beam overlap at a fixed laser fluence or increasing the laser fluence for a fixed number of laser shots. An apparent threshold for the onset of rapid enlargement of grain size was observed for processing at ∼90% overlap and fluences above 25 mJ/cm2. A maximum grain size of ∼280 nm was attained at a laser fluence of 30 mJ/cm2 and overlap of 93.75%, beyond which the grain size attained was smaller, and eventually, ablation was observed at an overlap of 97.5% and higher. These trends and observed surface morphology of annealed samples suggest that the crystallization mechanism is like sequential lateral solidification, similar to 800 nm-FLA and excimer laser annealing. Raman spectroscopic studies show that the degree of crystallization achieved with 400 nm-FLA is even higher than that of 800 nm-FLA. Cross-sectional scanning electron microscopic images indicate that the 100 nm-thick a-Si film is not fully crystallized. This can be explained by the much shorter penetration depth of 400 nm light than that of 800 nm light in a-Si.

Electrical Properties of Bottom Gate Poly-Si TFTs by NiSi2 Seed-Induced Lateral Crystallization and Its Applications

ABSTRACT In this paper, the electrical properties of bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by NiSi2 seed-induced lateral crystallization (SILC) and its applications are presented. Sequential lateral solidification (SLS), which is one of crystallization methods, is known to have poor electrical properties of TFTs with BG structures due to problems induced by laser. Therefore, the laser method cannot be used to well-developed production line of amorphous-Si (a-Si) TFT, resulting in large initial investment cost to change fabrication procedures. On the other hand, the BG poly-Si TFT by SILC (SILC-BGPS TFT) has basically compatible process flows with that of the a-Si TFT. The SILC-BGPS TFT exhibited threshold voltage of -3.9 V, steep subthreshold slope of 130 mV/dec, a high field-effect mobility of 129 cm2/Vs , and I on /I off ratio of ∼106.

Sequential Lateral Solidification of Silicon Thin Films on Cu BEOL-Integrated Wafers for Monolithic 3-D Integration

We demonstrate that wafers integrated with copper (Cu) Damascene interconnects are suitable substrates for the excimer laser crystallization of silicon thin films. This approach allows for the monolithic 3-D integration of transistors on the back end of line (BEOL) of silicon wafers for VLSI monolithic 3-D integration. This is supported by a 1-D finite-element method simulation of the integrated structure, which shows that, upon excimer laser irradiation, the temperature of the buried Cu layer stays below 320 °C, which is a favorable condition for monolithic 3-D integration. The crystallization of a 100-nm amorphous silicon layer on a 1-μm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric is demonstrated on a BEOL-integrated wafer. The Raman spectrum of the silicon layer after laser irradiation shows a polycrystalline peak centered around 513 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . Optical microscopy shows polycrystalline silicon with no physical damage of the Cu lines. The electrical characterization of the Cu buried layer, with and without undergoing the irradiation process, shows no variation or degradation in Cu conductivity.

Sequential lateral solidification of silicon thin films on low-k dielectrics for low temperature integration

We present the excimer laser crystallization of amorphous silicon on a low dielectric constant (low-k) insulator for very large scale integration monolithic 3D integration and demonstrate that low dielectric constant materials are suitable substrates for 3D integration through laser crystallization of silicon thin films. We crystallized 100 nm amorphous silicon on top of SiO2 and SiCOH (low-k) dielectrics, at different material thicknesses (1 μm, 0.75 μm, and 0.5 μm). The amorphous silicon crystallization on low-k dielectric requires 35% less laser energy than on an SiO2 dielectric. This difference is related to the thermal conductivity of the two materials, in agreement with one dimensional simulations of the crystallization process. We analyzed the morphology of the material through defect-enhanced microscopy, Raman spectroscopy, and X-ray diffraction analysis. SEM micrographs show that polycrystalline silicon is characterized by micron-long grains with an average width of 543 nm for the SiO2 sample and 570 nm for the low-k samples. Comparison of the Raman spectra does not show any major difference in film quality for the two different dielectrics, and polycrystalline silicon peaks are closely placed around 517 cm−1. From X-ray diffraction analysis, the material crystallized on SiO2 shows a preferential (111) crystal orientation. In the SiCOH case, the 111 peak strength decreases dramatically and samples do not show preferential crystal orientation. A 1D finite element method simulation of the crystallization process on a back end of line structure shows that copper (Cu) damascene interconnects reach a temperature of 70 °C or lower with a 0.5 μm dielectric layer between the Cu and the molten Si layer, a favorable condition for monolithic 3D integration.

Effects of Grain Size in Sequential Lateral Solidification Processed on Active Matrix Organic Light Emitting Diode Displays

In this work, we investigated the correlation between the spacing of primary grain boundaries in sequential lateral solidification (SLS) polycrystalline silicon and the brightness non-uniformity of active matrix organic light emitting diode panels. The oblique line is attributed both to the SLS method and the thin film transistor fabrication process. We found that the oblique line type of brightness non-uniformity disappeared when the spacing of primary grain boundaries is exactly the same in the individual transistor channel or when the non-uniform size is between 2.7 and 3.3 μ m( � Lg < ±10%) in active patterns. © 2014 The Electrochemical Society. [DOI: 10.1149/2.0071408ssl] All rights reserved.

High-Performance SLS Nanowire TFTs With Dual-Gate Structure

Gate-all-around (GAA) sequential-lateral-solidification (SLS) nanowire (NW) thin-film transistor (TFT) devices with single-gate and dual-gate structures are fabricated and characterized. Compared with planar SLS TFT, owing to only one perpendicular grain boundary in each NW channel, GAA SLS NW TFT with single-gate structure can exhibit better performances when operated at low gate/drain voltage. However, it suffers from an obvious kink effect when operated at high gate/drain voltage because of the local electrical fields located at the sharp corners in GAA structure. Via dual-gate structure design, it clearly improves the performance of TFT device, which thus has a lower leakage current, a higher ON/OFF ratio, and an improved kink effect as compared with single-gate TFTs by avoiding the perpendicular grain boundaries and reducing electrical fields near channel/drain junction regions. In addition, the device reliability, such as the threshold voltage shift, subthreshold swing, and transconductance degradation under dc hot-carrier stress, is apparently improved by the proposed structure.

Self-Heating and Kink Effects in SLS Single-Crystal-Like Nanowire Transistors

In this paper, the electrical characteristics of sequential-lateral-solidification (SLS) single-crystal-like nanowire (NW) poly-Si thin-film transistors (TFTs) with various gate structures are compared and comprehensively studied. The self-heating and kink effects of all SLS TFT devices with various gate structures are analyzed. Owing to the nanoscale nitride hard mask, each NW is easily transformed within one crystalline grain of the SLS poly-Si film with the regularly arranged grains; thus, each NW performs with a single-crystal-like device channel. Therefore, NW-type SLS TFTs with gate-all-around (GAA) and trigated (TRI) structures exhibit better electrical characteristics as compared with the conventional planar SLS TFTs. At moderate VGS and VDS biases, GAA devices exhibit better electrical characteristics. However, the self-heating effect and the local electric fields located at three sharp corners result in the severe degradation of electrical characteristics for GAA-SLS TFTs operated or stressed at high VGS and VDS biases.

A Physical Model for Grain-Boundary-Induced Threshold Voltage Variation in Polysilicon Thin-Film Transistors

Grain boundaries (GBs) in the channel region of polysilicon thin-film transistors (poly-Si TFTs) lead to large variations in the performance of TFTs (delay and power). In this paper, we present a physical model to characterize the GB-induced transistor threshold voltage variations considering not only the number but also the position and orientation of each GB in 3-D space. The estimated threshold voltage variations show a good agreement with experimental data and simulations performed by a numerical 3-D drift-diffusion device simulator. Using the proposed model, the impact of GBs on TFTs for various grain sizes, device sizes, and source–drain voltages is discussed in detail. Specifically, when the grain size is comparable to the size of the device, we observed that threshold voltage $(V_{\rm th})$ variations significantly increase, and $V_{\rm th}$ -distributions are non-Gaussian. Finally, using our model, we predict and demonstrate the GB-induced variations under different crystallization methods, such as sequential lateral solidification.

Simplified process for dot sequential lateral solidification of sputtered amorphous silicon thin films

In this work we demonstrated an improved method to obtain large grain Si islands matrix with the use of dot sequential lateral solidification. Amorphous Si thin films were deposited on glass plates and Si wafers with thin oxide layer by magnetron sputter. Dot sequential lateral solidification (dot-SLS) was applied on the selected areas of the films by a 248nm excimer laser. The laser beam was patterned by a stainless steel mask. The setup is designed such that the dot-SLS process can be carried out by having the samples move against the laser beam and patterned mask in a uniform motion, which greatly simplified the dot-SLS process. Single crystalline Si grains with an average size of 10μm were obtained and further characterized by an optical microscope, scanning electronic microscope (SEM) and Raman spectrometer. The research work showed a simple method to achieve single crystalline Si islands matrix, which could be used as a seed layer to produce large grain sized Si films for high efficiency polycrystalline Si thin film solar cells and high performance flat panel displays.

High performance of ultralow temperature polycrystalline silicon thin film transistor on plastic substrate

A high performance ultralow temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) was obtained on a plastic substrate using the optimization of a triple layered buffer process for a suppression the damage on plastic substrate during laser dopant activation, the high quality SiO2 interface layer formation between the gate dielectric film and the poly-Si film using plasma oxidation, and a successful crystallization of large grain poly-Si films with a sequential lateral solidification (SLS) method. High performances with field effect mobilities of 180 and 62cm2V−1s−1, threshold voltages of 1.4 and −1.6V and sub-threshold swings of 0.78 and 0.92V/decade were obtained for n-channel metal–oxide-semiconductor (nMOS) and p-channel metal–oxide-semiconductor (pMOS) TFT on plastic substrate, respectively.

Crystallization and surface texturing of amorphous-Si induced by UV laser for photovoltaic application

The DPSS Nd:YVO4 UV laser is used to anneal amorphous silicon (a-Si) film to achieve crystallization and nano-dome surface texturing simultaneously in a one-step annealing process. With pulse energy of 380 mJ/cm2 and repetition rate of 20 kHz, the a-Si can be crystallized by the sequential lateral solidification process, which is evidenced by both SEM characterization and Raman spectra. In addition, the nano-dome like structure is confirmed by AFM characterization, which can lead to ∼200% boost in terms of light absorption as measured by UV-Visible - Near-infrared scanning spectrophotometer. This study highlights the great potential of Nd:YVO4 UV laser for its application in thin film Si solar cell industry to improve the film quality and light trapping capability.

P-Type Tunneling Transistors with Polycrystalline Silicon by Sequential Lateral Solidification Growth Technique

p-Type tunneling transistors with polycrystalline silicon were fabricated, and their electrical characteristics were studied. The temperature dependence of the tunneling current proves that the current of our device is indeed due to the band-to-band tunneling effect, rather than to the avalanche effect. The reliability of the polycrystalline silicon (poly-Si) tunneling transistors with a grain direction effect due to the active layer formed by the sequential lateral solidification (SLS) growth technique was examined. The device with a channel parallel to the grains has a high band-to-band tunneling current, low leakage current, and threshold voltage stability with constant current stress. Promising poly-Si tunneling transistors with a gate-controlled current and a low off-current have attracted attention for some applications such as in display backplanes, three-dimensional integrated circuits (3D-ICs), and microwave circuits in the future.

P-Type Tunneling Transistors with Polycrystalline Silicon by Sequential Lateral Solidification Growth Technique

p-Type Tunneling Transistors with Polycrystalline Silicon by Sequential Lateral Solidification Growth Technique

Electrical activation in boron doped polycrystalline Si formed by sequential lateral solidification

We have investigated the electrical activation in boron doped poly-Si using Hall measurement, 4-point probe, and secondary ion mass spectroscopy. Through doping was conducted using a mass-separated ion implanter with acceleration energies from 20 to 35 keV at doses ranging from 1 × 10 15/cm 2 to 4 × 10 15/cm 2, followed by isothermal rapid-thermal-annealing at temperatures ranging from 550 to 650 °C. The substrates used were poly-Si, produced by two-shot sequential lateral solidification. Reverse annealing, in which a continuous loss of charge carriers occurs, was observed in boron doped poly-Si. We found that implantation conditions play a critical role on dopant activation as well as annealing conditions. We observed that a certain implantation condition does exist where the sheet resistance is not changed upon activation annealing. Damage recovery encountered in activation annealing seems to be closely related to a reverse-annealing phenomenon. We assume that the defect-concentration profile would be more important to activation behavior of poly-Si than integrated defect-density accumulated in the silicon layer.

Resolving Bulk and Grain Boundary Transport Properties of TiO2 Thin Films Enabled by Laser‐Induced Anisotropic Morphology

Precise deconvolution of grain and grain boundary contributions to the overall impedance of TiO2 thin films is achieved by impedance spectroscopy measurements of textured films with elongated grains obtained by laser-induced melting and sequential lateral solidification. The ability to engineer the grain morphology of electroceramic films provides opportunities for new designs of ferroelectric memories, piezoelectric microsensors and microactuators, optical waveguides, and other devices. Detailed facts of importance to specialist readers are published as ”Supporting Information”. Such documents are peer-reviewed, but not copy-edited or typeset. They are made available as submitted by the authors. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

Improved Uniformity of Sequential Lateral Solidification Thin-Film Transistors

The uniformity of threshold voltage (Vth) in sequential lateral solidification (SLS) thin-film transistors (TFTs) is investigated. Some SLS TFTs have higher Vth values than others, which causes problems in applications requiring a high level of TFT uniformity such as active-matrix organic light-emitting diode displays. Focused ion beam observations revealed that all TFTs with high Vth values had protrusions 3000- 7000 Å from the junction. Using a smart tilted-channel structure decreased the Vth variation to less than 0.2 V.

15.2: Green Laser Sequential Lateral Solidification G‐SLS Process for AMOLED Applications

AbstractThis paper presents a novel green laser sequential lateral solidification G‐SLS process for AMOLED applications. G‐SLS utilizes a high frequency pulsed green laser and 2D mask patterns to manipulate the microstructure of crystallize Si films. Mask patterns have been optimized to obtain uniform microstructure of the crystallized Si films at the overlap region. Thin film transistors based on G‐SLS processed Si films have mobility of 150.72 cm2/V‐sec and a sub‐threshold swing of 0.20V/dec. 14″ qFHD AMOLEDs have been fabricated using the G‐SLS process. The advantages and issues of G‐SLS technology will be further discussed.

Electrical characterization of polycrystalline silicon thin film transistors crystallized by a new alignment sequential lateral solidification process

In the conventional sequential lateral solidification (SLS) method for polycrystalline silicon thin-film transistors (poly-Si TFTs), as a starting process in general, one just performs a basic pre-alignment of the substrate on the stage and applies laser irradiation for a whole substrate area scan. Therefore, each thin-film transistor (TFT) has different grain boundary (GB) locations in a corresponding channel region. The number of GBs in the channel also varies from one to two, which can give rise to electrically non-uniform TFT characteristics and an image quality deterioration of the panel. We developed a new alignment SLS method for controlling the GB location in the TFT channel region, allowing us to locate the GB at the same position in the channel region of each TFT. We fabricated TFT by applying the new alignment SLS process and compared the TFT electrical characteristics between a normal SLS method and the new one. We also analyzed degradation phenomena under hot carrier stress conditions for lightly doped drain n-type metal oxide semiconducting field effect transistors.

Voltage Noise Characteristics of Polysilicon P-I-N Diodes

In this paper, voltage noise of lateral polysilicon p-i-n diodes, biased at constant current levels, is studied. The polysilicon film that forms the active material of the p-i-n diodes was prepared by the crystallization of amorphous silicon either by the solid phase crystallization (SPC) or the sequential lateral solidification (SLS) method; two different thicknesses of 100 and 50 nm were also investigated. Measurement results of the voltage noise at frequency bandwidth from 500 Hz to 1 MHz for polysilicon p-i-n diodes with different crystallization methods and active material thicknesses are presented. The effects of grain size, i-region geometry, and the biasing current on the voltage noise of p-i-n diodes are studied. Furthermore, different methods of improving the voltage noise of p-i-n diodes are also discussed, and experimental results are demonstrated.

New Bidirectional T-Shaped Triple-Gate n-Type Polycrystalline Silicon Thin-Film Transistors Formed by Low-Temperature Sequential Lateral Solidification Process to Reduce of Kink Effects

A new bidirectional T-shaped triple-gate device structure, which suppresses the kink effect of sequential lateral solidification (SLS)-processed polycrystalline silicon thin film transistors (poly-Si TFTs), is proposed and fabricated without any additional process. The proposed poly-Si TFTs have a lateral grain growth in channels, similar to TFTs fabricated by SLS or continuous wave (CW) laser crystallization. The whole current flow of the proposed device is mainly affected by the grain boundaries of lateral grain growth. The bidirectional T-shaped triple-gate structure has incorporated a channel located parallel to the lateral grain growth direction, and the another channel located vertically to the lateral grain growth direction. It is verified from experimental and simulation results that the proposed bidirectional T-shaped triple-gate TFT effectively suppresses the kink current of poly-Si TFT with anisotropic mobility in the triple-gate structure. Our experimental results show that the proposed bidirectional T-shaped triple-gate TFT can suppress the kink effect more effectively than the conventional dual-gate TFT, and L-shaped dual-gate TFT and can improve reliability under the high drain bias condition. The proposed device demonstrates that bidirectional operation is possible for integrated circuits compared with the L-shaped dual-gate structure that shows only fixed one-directional behavior. The proposed device exhibits a very low output conductance in the saturation regime, and this result indicates that higher output resistance is obtained in the proposed bidirectional T-shaped triple-gate TFT.