Electrical characterization of polycrystalline silicon thin film transistors crystallized by a new alignment sequential lateral solidification process

Abstract

In the conventional sequential lateral solidification (SLS) method for polycrystalline silicon thin-film transistors (poly-Si TFTs), as a starting process in general, one just performs a basic pre-alignment of the substrate on the stage and applies laser irradiation for a whole substrate area scan. Therefore, each thin-film transistor (TFT) has different grain boundary (GB) locations in a corresponding channel region. The number of GBs in the channel also varies from one to two, which can give rise to electrically non-uniform TFT characteristics and an image quality deterioration of the panel. We developed a new alignment SLS method for controlling the GB location in the TFT channel region, allowing us to locate the GB at the same position in the channel region of each TFT. We fabricated TFT by applying the new alignment SLS process and compared the TFT electrical characteristics between a normal SLS method and the new one. We also analyzed degradation phenomena under hot carrier stress conditions for lightly doped drain n-type metal oxide semiconducting field effect transistors.