Sensitive Nodes Research Articles

Hide and Seek: Outwitting Community Detection Algorithms

Community affiliation of a node plays an important role in determining its contextual position in the network, which may raise privacy concerns when a sensitive node wants to hide its identity in a network. Oftentimes, a target community seeks to protect itself from adversaries so that its constituent members remain hidden inside the network. The current study focuses on hiding such sensitive communities so that the community affiliation of the targeted nodes can be concealed. This leads to the problem of community deception, which investigates the avenues of minimally rewiring nodes in a network so that a given target community maximally hides from a community detection algorithm (CDA). We formalize the problem of community deception and introduce Network deception using permanence loss (NEURAL), a novel method that greedily optimizes a node-centric objective function to determine the rewiring strategy. Theoretical settings pose a restriction on the number of strategies that can be employed to optimize the objective function, which in turn reduces the overhead of choosing the best strategy from multiple options. We also show that our objective function is submodular and monotone. When tested on both synthetic and seven real-world networks, NEURAL is able to deceive six widely used CDAs. We benchmark its performance with respect to four state-of-the-art methods on four evaluation metrics. In addition, our qualitative analysis on three other attributed real-world networks reveals that NEURAL, quite strikingly, captures important metainformation about edges that otherwise could not be inferred by observing only their topological structures.

Wireless sensor network’s localization based on multiple signal classification algorithm

Wireless sensor networks (WSNs) are a number of sensitive nodes senses a physical phenomenon at the position of their deployment then sends information to the base station to take appropriate operation. (WSNs) are used in many applications such track military targets, discover fires, study natural phenomena such as earthquakes, humidity, heat, etc. The nodes are spread in large areas and it is difficult to locate them manually because they are published randomly by planes or any other method and since the information received from sensitive nodes is useless without knowing their location in this case a problem resulted in the positioning of the nodes. So it unacceptable to equip each sensor node with global position system (GPS) due to various problems such as raises cost and energy consumption. In this paper explained a non-GPS technique to self-positioning of nodes in (WSNs) by using the multiple signal classification (MUSIC) algorithm to determine the position of the active sensor through estimated the direction of arrival (DOA) of the node signal. Then modified MUSIC algorithm (M-MUSIC) to solve the problem of coherent signal. MATLAB program successfully used to simulate the proposed algorithm.

Impact of negative bias temperature instability on single event transients in scaled logic circuits

AbstractAltering the performance of single transistors and integrated circuits at nominal operating conditions over time, as well as soft errors, are serious reliability issues for integrated CMOS circuits, especially when used in space applications. In principle, the effect of soft errors becomes even more critical if the circuit performance degrades over time. To address this detrimental behavior, the impact of performance degradation due to NBTI on the soft error susceptibility of integrated circuits is analyzed thoroughly. For this, we analyze the critical charge sensitivity of the two‐input NAND gate and NOR gate for different operating temperatures at stress times up to 3 years. The results show that the critical charge decreases with the temperature and strongly depends on the input states. Next, we validate the results employing the c17 ISCAS'85 benchmark suite, employing the PTM model with the HSPICE to estimate the soft error at the sensitive nodes. The critical charge is observed to be sensitive to the selected supply voltage and device temperature and thus provides a good measure for the soft error susceptibility with respect to NBTI at various operation conditions.

AEROSPACE APPLICATIONS IN NANO SCALE CMOS TECHNOLOGY USING 12T MEMORY CELL

Semiconductor sizes and the gaps between them are decreasing with the advancement of technology. This means that SRAM cells used in aerospace applications are more vulnerable to soft-error when the fundamental charge of the fragile nodes decreases. A single-event upset (SEU) caused by a radiation particle striking a sensitive node in a conventional 6T SRAM cell could lead to data inversion. To lessen the consequences of SEUs, this study proposes the use of a Soft-Error-Aware Read-StabilityEnhanced Low-Power 12T (SARP12T) SRAM cell. The performance of SARP12T is evaluated in relation to other recently released soft-error-aware SRAM cells, such as QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T. In the event that a radiation attack flips the values of the sensitive nodes in SARP12T, the data may still be recoverable. When a storage node pair initiates a singleevent multi-node upset (SEMNU), SARP12T is resilient enough to endure it. During read operations, the bitline makes it simple to reach the '0' storing memory nodes in the suggested cell, and it also makes them very resilient to interruptions. In terms of energy usage, SARP12T is the most effective holding strategy. SARP12T outperforms competing cells in terms of write performance, and its write latency is much decreased. To achieve all of these advantages, the suggested cell very slightly increases read latency and read/write energy.

Efficient architecture for deep neural networks with heterogeneous sensitivity

In this study, we present a neural network that consists of nodes with heterogeneous sensitivity. Each node in a network is assigned a variable that determines the sensitivity with which it learns to perform a given task. The network is trained via a constrained optimization that maximizes the sparsity of the sensitivity variables while ensuring optimal network performance. As a result, the network learns to perform a given task using only a few sensitive nodes. Insensitive nodes, which are nodes with zero sensitivity, can be removed from a trained network to obtain a computationally efficient network. Removing zero-sensitivity nodes has no effect on the performance of the network because the network has already been trained to perform the task without them. The regularization parameter used to solve the optimization problem was simultaneously found during the training of the networks. To validate our approach, we designed networks with computationally efficient architectures for various tasks such as autoregression, object recognition, facial expression recognition, and object detection using various datasets. In our experiments, the networks designed by our proposed method provided the same or higher performances but with far less computational complexity.

A comparison study on electromagnetic susceptibility of current reference circuits with scaling-down technologies and schemes

This paper studies the effects of process node and circuit schemes on the electromagnetic susceptibility (EMS) of current reference circuits. Three reference circuits using PDSOI with technology node of 0.5 μm (VREF50), 0.35 μm (VREF33) and 0.18 μm (VREF18) are used. VREF50 has an additional CASCODE structure to achieve a PSRR enhancement. The test results show that when the electromagnetic interference (EMI)is injected into the terminals VDD and VSS, the reference currents in both of the three circuits exhibit a negative shift. The main reason is that the drain voltage of the transistor close to the terminal VDD fluctuates greatly, causing a deviation from the saturation to the linear region from time to time, hence reducing the average value of the current. The higher voltage margin with the large process node, the stronger the immunity of the reference circuit to EMI. It is worth noting that the CASCODE structure has a negative effect on low frequency large-signal EMI. Therefore, VREF50 and VREF33 have the similar EMS. In a higher frequency range, the parasitic effect brought by the CASCODE structure becomes more serious, which increases the high-frequency impedance of the circuit. Finally, simulation results imply that the immunity level is improved by decreasing bypass capacitor between the sensitive node and the VDD to reduce the EMI injection, and replacing the nonlinear device by a positive temperature coefficient resistor to improve the circuit linearity.

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

Single-Event Transients in an IEEE 802.15.4 RF Receiver for Wireless Sensor Networks.

This paper presents a procedure to analyse the effects of radiation in an IEEE 802.15.4 RF receiver for wireless sensor networks (WSNs). Specifically, single-event transients (SETs) represent one of the greatest threats to the adequate performance of electronic communication devices in high-radiation environments. The proposed procedure consists in injecting current pulses in sensitive nodes of the receiver and analysing how they propagate through the different circuits that form the receiver. In order to perform this analysis, a Complementary Metal Oxide Semiconductor (CMOS) low-IF receiver has been designed using a 0.18 μm technology from the foundry UMC. In order to analyse the effect of single-event transients in this receiver, it has been studied how current pulses generated in the low-noise amplifier propagate down the receiver chain. The effect of the different circuits that form the receiver on this kind of pulse has been studied prior to the analysis of the complete receiver. First, the effect of SETs in low-noise amplifiers was analysed. Then, the propagation of pulses through mixers was studied. The effect of filters in the analysed current pulses has also been studied. Regarding the analysis of the designed RF receiver, an amplitude and phase shift was observed under the presence of SETs.

Smart Cities

Abstract This paper is based on the paradigm that a smart city is a part of the intellectual framework of second-order cybernetics and considers social communication in terms of the management and use of different data channels. Planning as a political practice is replaced by environmentally-behavioral control, in which subjectivity is articulated above-individually (permeating the city with sensitive nodes) and infra-individually (transforming citizens into sensitive nodes). This leads us to the research question: how to focus on the social relations and processes of the smart urbanization which are based on the second order cybernetic approach? The smart city is understood as a complex mechanism, where one begins to realize the often-unintended human, environmental, social and economic consequences of a technological and engineering-led approach. The latest thinking and smart urban projects are aimed at comprehending smart and/or sustainable infrastructure as a network between places and people in order to create a more sustainable, healthy and resilient future for different groups of citizens (from young people to seniors). Municipality strategies need to address global socio-economic factors, processes of innovation with new technology, constant adaptation in public and private sector organisations and the diversity of qualified resources.

Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance

Double-node upsets induced by the charge sharing effects are emerging as a major reliability issue in nanometer latch design. Although the existing robust latches can provide a good tolerance for double-node upsets, the implementation of these hardened latches incurs in considerable hardware penalties in terms of delay, area, and power, because they rely on traditional hardening techniques such as space redundancy. In this paper, a novel low-complexity (with respect to hardware redundancy in terms of area, delay, and power) radiation hardened (RH) latch is proposed; this latch is based on the dual interlocked storage cell (DICE). Based on the radiation upset mechanism, in particular the upset polarity of the transient pulse, the proposed RH latch can effectively reduce the number of protected nodes (sensitive nodes), as well as the number of transistors, thus reducing circuit overhead. At the same, a single node upset in any sensitive node and a double-node upset in any sensitive node pair can be recovered, because at least two stable nodes can retain the values even when a double-node upset occurs. The results are based on mapping designs to TSMC 65 nm commercial CMOS process design kit (PDK) and demonstrate that the proposed RH latch incurs in significant reductions in terms of propagation delay, circuit area, and power-delay-area product (PDAP), compared with existing hardened latches. The tolerance functionality of the proposed latch is successfully validated by fault injection. In addition, the impact of variations and process corners is assessed using Monte Carlo (MC) simulation. The simulation results confirm that the proposed latch can also tolerate all upsets, even under extreme values of process variations.

Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits.

It has been known that negative feedback loops (internal and external) in a SiGe heterojunction bipolar transistors (HBT) DC current mirrors improve single-event transient (SET) response; both the peak transient current and the settling time significantly decrease. In the present work, we demonstrate how radiation hardening by design (RHBD) techniques utilized in DC bias blocks only (current mirrors) can also improve the SET response in AC signal paths of switching circuits (e.g., current-mode logic, CML) without any additional hardening in those AC signal paths. Four CML circuits both with and without RHBD current mirrors were fabricated in 130 nm SiGe HBT technology. Two existing RHBD techniques were employed separately in the current mirrors of the CML circuits: (1) applying internal negative feedback and (2) adding a large capacitor in a sensitive node. In addition, these methods are also combined to analyze the overall SET performance. The single-event transients of the fabricated circuits were captured under the two-photon-absorption laser-induced single-event environment. The measurement data clearly show significant improvements in SET response in the AC signal paths of the CML circuits by using the two radiation hardening techniques applied only in DC current mirrors. The peak output transient current is notably reduced, and the settling time upon a laser strike is shortened significantly.

Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications

Conventional radiation-hardened cells of static random access memory (SRAM) are not robust enough in 28 nm technology, due to partial immunity of single-event upset (SEU) effect (Quatro-based cells) or insufficient critical charges in sensitive nodes (conventional stacked cells). The reduction of read noise margin (RNM) at the low supply voltage (VDD) confines these cells from low VDD applications. We propose a novel interleaving stacked-14T (ILS-14T) cell which prevents voltage transient from propagating to other redundancies. The ILS-14T cell can be resilient to both 0–1 and 1–0 upsets by injecting 12 mA in sensitive nodes. The critical charges of the ILS-14T cell are substantially larger than most other hardened cells at VDD from 0.3 to 0.9 V. The RNM of the ILS-14T cell is two times of most Quatro-based cells at 0.3 V VDD and larger than most cells at 0.6 and 0.9 V VDD. The area of occupation is 334% of the conventional 6T cell, which equals other 14T cells. The static–dynamic decoder array with 20%–40% area penalty and 116%–132% delay of rising edge, when compared with the conventional one, reduces the read failure rate by preventing single event transients (SETs) from propagating to unexpected word lines (WLs).

Deep neural networks with a set of node-wise varying activation functions

In this study, we present deep neural networks with a set of node-wise varying activation functions. The feature-learning abilities of the nodes are affected by the selected activation functions, where the nodes with smaller indices become increasingly more sensitive during training. As a result, the features learned by the nodes are sorted by the node indices in order of their importance such that more sensitive nodes are related to more important features. The proposed networks learn input features but also the importance of the features. Nodes with lower importance in the proposed networks can be pruned to reduce the complexity of the networks, and the pruned networks can be retrained without incurring performance losses. We validated the feature-sorting property of the proposed method using both shallow and deep networks as well as deep networks transferred from existing networks.

Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications

Soft error in SRAM cell is one of the major reliability concern under aerospace radiation environment. A soft error occurs in SRAM cell due to charged particle strikes on sensitive nodes. In this paper a radiation hardened asymmetric 10T (AS10T) SRAM cell is presented to enhance the soft error hardening. The proposed cell uses read decoupled path to improve read static noise margin (RSNM) and voltage booster connected between storage nodes to improve node capacitance and hence enhanced radiation hardening. The proposed AS10T cell has a 75.83% higher critical charge as compared to 6T SRAM cell. For validation of soft error hardening of the proposed cell soft error rate ratio with supply voltage and temperature change is calculated and it is found that the AS10T has 6.41× and 3.2× less soft error rate ratio compared to 6T SRAM cell respectively. To better assess soft-error resilience and performance of the cell we introduce reliability stability to energy area product (RSEAP) ratio as a performance metric. Our analysis indicates that AS10T cell has 2.83× 1.6× and 1.36× higher RSEAP as compared to 6T RD8T and AS8T SRAM cells respectively.

Bias Temperature Instability Aware and Soft Error Tolerant Radiation Hardened 10T SRAM Cell

In this paper, we propose an asymmetric radiation-hardened 10T (AS10T) SRAM cell and analyze the impact of bias temperature instabilities (BTI) on the single event upset of the modified structure. For this, we make use of a read decoupled circuit to improve the stability of the reading cycle, and a charge booster circuit to increase the critical charge at the sensitive node of the SRAM cell. First, we compare the noise margin of several reference cells and can clearly observe that the read static noise margin (RSNM) of AS10T is 3.25× higher than as can be achieved for the 6T SRAM cell. This improvement is due to the read decoupled path used for the read operation. To analyze the soft-error hardening, we calculate the critical charge and observe that the critical charge of the proposed AS10T cell exceed the same parameter of other SRAM cells. Further, we perform critical charge simulations and stability analysis considering BTI and observe that the AS10T SRAM cell is also less affected by BTI as the reference cells.

Single-event-upset effect simulation of HfO<sub>2</sub>-based ferroelectric field effect transistor read and write circuits

Ferroelectric field effect transistor (FeFET) is a promising memory cell for space application. The FeFET can achieve non-destructive reading, and has the advantages of simple structure and high integration. Ferroelectric thin film’s size effect, retention performance and radiation resistance of ferroelectric thin films directly determine the performances of FeFET devices. The HfO<sub>2</sub> is widely used as a dielectric in complementary metal oxide semiconductor (CMOS) device and can solve the common integration problems for ferroelectric materials due to its CMOS compatibility. When the HfO<sub>2</sub>-based FeFETs are applied to aerospace electronics, the effects of various radiation particles need to be considered. The HfO<sub>2</sub>-based FeFET memory is still in the experimental stage, and there are no products of HfO<sub>2</sub>-based FeFET chips available from the market, so it is difficult to carry out experimental research on its single particle effect In the case of lacking the finished products of HfO<sub>2</sub>-based FeFET devices, using the device-hybrid simulation method to study the HfO<sub>2</sub>-based FeFET single-particle effect is a necessary and feasible content for the research on HfO<sub>2</sub>-based FeFET single-particle effects. In this paper, the device-circuit simulation method is used to build a read-write circuit of HfO<sub>2</sub>-based ferroelectric field-effect transistor. The change of read and write data after a single particle is incident on a ferroelectric field effect transistor memory cell and a sensitive node of a peripheral sense amplifier is studied, and the internal mechanism of read and write data fluctuation is analyzed. The results show that when high-energy particles enter into the drain of the ferroelectric memory cell in the read-write circuit, the memory cells in the “0” state generate electron-hole pairs, which accumulate inside the device, causing the gate electric field strength and ferroelectricity to increase, and the memory cell in the “1” state has a large fluctuation in the output transient pulse voltage signal due to the charge injection of the source, indicating that the ferroelectric memory cell has a good performance against particle flipping; when high-energy particles enter into the amplifier’s sensitive node, a collection current is generated, causing the amplifier in the state of reading “0” to turn on, and the output data to fluctuate. Owing to the fluctuation time being only 0.4 ns, the data does not have single-particle flipping energy under normal readout, and the HfO<sub>2</sub>-based FeFET read-write circuit has excellent resistance to single particles. When two beams of high-energy particles act on the drain of a ferroelectric memory cell successively in a time interval of 0.5 ns, the output data signal fluctuates more than in the case of a single beam of high-energy particles, and the final output voltage difference in the reading and writing “1” state becomes smaller.

Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology

Multiple-node upsets (MNUs) caused by charge sharing effects are dramatically increasing in advanced nanoscale digital latches. Consequently, the robust latches against MNU cases are increasingly important. Although some existing robust latches are designed to recover MNU cases, they incur significant hardware redundancy and more sensitive nodes due to only depending on multiple circuit instances (e.g., C-elements (CEs)). In order to obtain a balance between high tolerance capability and low overheads, in this paper, we propose a novel radiation hardened latch (RHL) based on the polarity of the radiation-induced voltage pulse (positive or negative pulse). The proposed latch is capable of tolerating any possible single node upset (SNU) and MNU cases in all considered nodes while manifesting fewer transistors and sensitive nodes. The timing (transparent and hold) function and reliability are successfully verified by simulation in TSMC 65nm bulk CMOS process. In addition, the results of the cost comparison have illustrated that the proposed RHL latch has a moderate area and power dissipation, but provides significant benefit in terms of both delay and power-delay-area-product (PDAP) among the alternative latches.

Design of Radiation Hardened Complementary Folded Cascode Amplifier

Sensitive Node Active Charge Cancellation technique (SNACC) is applied on the Complementary Folded Cascode amplifier (CFC) to study single event transients (SET) on this circuit. A Built-In-Detector (BID) is connected to the circuit to sense the variations of the currents in the op-amp and to represent their input and output characteristics. Two circuits are designed with and without SNACC, using UMC_CMOS_180nm process in cadence virtuoso environment. This work analyses to identify the effectiveness of Radiation Hardening By Design (RHBD) technique by comparing radiation sensitive and radiation hardened CFC amplifier.

Single-Event Transients in SiGe HBTs Induced by Pulsed X-Ray Microbeam

This article presents an experimental study of single-event transients (SETs) induced by pulsed X-rays in SiGe heterojunction bipolar transistors (HBTs). Device-level transient data and circuit-level upset data from pulsed X-rays are analyzed and compared to those of heavy-ions. 3-D TCAD modeling is utilized to understand the source of the differences in the transients. The transient peak from the ion-shunt effect is not present in pulsed X-ray transients due to its large spot size and slow pulse transition, both of which lead to lower peak carrier densities. The diffusion “tail,” typically present in transients measured from SiGe HBTs, also differs between the two sources. The charge collection of X-ray has a linear correlation with surface linear energy transfer (LET) across the photon energies of 8–12 keV. For a similar surface LET, the impinging heavy-ion pushes the subcollector-substrate junction boundaries of the SiGe HBT deeper, resulting in higher charge collection. Single-event upset (SEU) screening of shift-registers shows that X-ray can detect device sensitive nodes smaller than the beam.

NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-basedlook-up table for ultralow power and highly reliable FPGA designs

Complementary metal oxide semiconductor (CMOS) downscaling leads to various challenges, such as high leakage current and increase in radiation sensitivity. To solve such challenges, hybrid MTJ/CMOS technology-based design has been considered as a very promising approach thanks to the high speed, low power, good scalability, and full compatibility of magnetic tunnel junction (MTJ) devices with CMOS technology. One important application of MTJs is the efficient utilization in building nonvolatile look-up tables (NV-LUTs) used in reconfigurable logic. However, NV-LUTs face severe reliability issues in nanotechnology due to the increasing process variations, reduced supply voltage, and high energetic particle strike at sensitive nodes of CMOS circuits. This paper proposes a nonvolatile radiation-hardened look-up table (NVRH-LUT) for advanced reconfigurable logic. Compared with previous works, the proposed NVRH-LUT is fully robust against single-event upsets and also single-event double-node upsets that are among the main reliability-challenging issues for NV-LUTs. Results have shown that NVRH-LUT not only provides increasing reliability and reduced bit error rate but also offers low delay and low energy consumption.