Abstract
In this paper, we propose an asymmetric radiation-hardened 10T (AS10T) SRAM cell and analyze the impact of bias temperature instabilities (BTI) on the single event upset of the modified structure. For this, we make use of a read decoupled circuit to improve the stability of the reading cycle, and a charge booster circuit to increase the critical charge at the sensitive node of the SRAM cell. First, we compare the noise margin of several reference cells and can clearly observe that the read static noise margin (RSNM) of AS10T is 3.25× higher than as can be achieved for the 6T SRAM cell. This improvement is due to the read decoupled path used for the read operation. To analyze the soft-error hardening, we calculate the critical charge and observe that the critical charge of the proposed AS10T cell exceed the same parameter of other SRAM cells. Further, we perform critical charge simulations and stability analysis considering BTI and observe that the AS10T SRAM cell is also less affected by BTI as the reference cells.
Highlights
Due to rapid scaling of integrated devices and circuits, reliability issues have become more serious concerns in modern applications
The results reveal that the asymmetric radiation-hardened 10T (AS10T) SRAM cell exhibits an overall enhanced soft error immunity because of an increased minimum amount of charge required to flip the stored data
This paper presents a radiation-hardened asymmetric a 10T (AS10T) SRAM cell to enhance the soft error hardening, considering aging effects like bias temperature instabilities
Summary
Due to rapid scaling of integrated devices and circuits, reliability issues have become more serious concerns in modern applications. The 6T SRAM cell exhibits a reduced critical charge, which is not suitable for the applications where perturbations due to high energy particles are more likely To circumvent these limitations Chang et al [4] proposed read decoupled 8T SRAM cell (RD8T). The read SNM was improved, the RD8T cell is still affected by external radiation at the same level of sensitivity as the 6T SRAM cell, no improvement in the soft error hardening could be achieved. SRAM cell is presented in Reference [6] This cell exhibits soft error hardening but requires a large area. Based on the above discussions there is a high demand for optimization of the SRAM cells, to improve their soft error resilience as well as to improve the RSNM while avoiding to increase the required chip area, ensuring high signal integrity, and low power consumption of the SRAM cell
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