Abstract
Complementary metal oxide semiconductor (CMOS) downscaling leads to various challenges, such as high leakage current and increase in radiation sensitivity. To solve such challenges, hybrid MTJ/CMOS technology-based design has been considered as a very promising approach thanks to the high speed, low power, good scalability, and full compatibility of magnetic tunnel junction (MTJ) devices with CMOS technology. One important application of MTJs is the efficient utilization in building nonvolatile look-up tables (NV-LUTs) used in reconfigurable logic. However, NV-LUTs face severe reliability issues in nanotechnology due to the increasing process variations, reduced supply voltage, and high energetic particle strike at sensitive nodes of CMOS circuits. This paper proposes a nonvolatile radiation-hardened look-up table (NVRH-LUT) for advanced reconfigurable logic. Compared with previous works, the proposed NVRH-LUT is fully robust against single-event upsets and also single-event double-node upsets that are among the main reliability-challenging issues for NV-LUTs. Results have shown that NVRH-LUT not only provides increasing reliability and reduced bit error rate but also offers low delay and low energy consumption.
Highlights
With recent acceleration of advanced complementary metal oxide semiconductor (CMOS) downscaling, sensitivity to radiation effects is increasing [1, 2]
To overcome vulnerability against single-event upset (SEU) effects, we propose a radiation-hardened precharge sense amplifier (PCSA) (RH-PCSA) circuit
To inject the SEU fault into the simulated spin transfer torque (STT)-LUTs, we used the model presented in [36], in which an SE hit could be simulated at the output of the STT-LUT using a double exponential current source with the behavior of Eq 2: Iinj (t) =
Summary
With recent acceleration of advanced complementary metal oxide semiconductor (CMOS) downscaling, sensitivity to radiation effects is increasing [1, 2]. 2. Related works To reduce the leakage power of the SRAM-based FPGA devices and protect them against particle strikes, many practical solutions for FPGA logic circuits based on STTRAM technology have been proposed. Related works To reduce the leakage power of the SRAM-based FPGA devices and protect them against particle strikes, many practical solutions for FPGA logic circuits based on STTRAM technology have been proposed They can be classified into two significant categories: a) single-sense amplifier STT-LUT and b) multisense amplifier STT-LUT. Different STT-LUT circuits have already been proposed in the literature (e.g., [15,16,17,18,19,20,21,22,23,24]) They suffer from long read delays and less reliability (due to such failures as decision failure, write failure, and read disturb). We propose a novel STT-LUT that achieves significant impact on the area (the reduction of transistor count), speed (the reduction of path-length), and reliability (the reduction of path-length, path-transistor count, and robustness against SEUs) compared to the previously proposed STT-LUTs
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