Semiconductor Process Development Research Articles

The Use of Artificial Intelligence and Machine Learning in Soft X-ray Technology for Advanced Semiconductor Process Development and Control

The Use of Artificial Intelligence and Machine Learning in Soft X-ray Technology for Advanced Semiconductor Process Development and Control

A triple-node-upset self-recoverable design based on Schmitt-triggers and C-elements

As the semiconductor process development, it is shrinking rapidly for the distance of adjacent transistors in integrated circuits (ICs). Hence, latches are increasingly vulnerable to multiple-node-upset (MNU). To effectively mitigate MNU while keeping lower power consumption and delay, this paper proposed a latch design (namely CS-TNURL). The latch consists of four C-elements (CEs), four Schmitt-triggers (STs), seven transmission gates (TGs), and is capable of triple-node-upset (TNU) self-recovery. Besides, this latch uses fewer transistors and clock gating technique, which results in lower power consumption and D-Q delay. Compared with existing latches with TNU self-recoverability, the simulation has shown the proposed latch reduces power consumption by 70 %, delay by 10.62 %, area overhead by 29.71 %, and the power-delay-product (PDP) by 70.34 % on average, respectively. Additionally, the estimation of process, voltage, and temperature (PVT) variation indicated CS-TNURL has a moderate sensitivity towards the PVT variation.

Human–machine collaboration for improving semiconductor process development

One of the bottlenecks to building semiconductor chips is the increasing cost required to develop chemical plasma processes that form the transistors and memory storage cells1,2. These processes are still developed manually using highly trained engineers searching for a combination of tool parameters that produces an acceptable result on the silicon wafer3. The challenge for computer algorithms is the availability of limited experimental data owing to the high cost of acquisition, making it difficult to form a predictive model with accuracy to the atomic scale. Here we study Bayesian optimization algorithms to investigate how artificial intelligence (AI) might decrease the cost of developing complex semiconductor chip processes. In particular, we create a controlled virtual process game to systematically benchmark the performance of humans and computers for the design of a semiconductor fabrication process. We find that human engineers excel in the early stages of development, whereas the algorithms are far more cost-efficient near the tight tolerances of the target. Furthermore, we show that a strategy using both human designers with high expertise and algorithms in a human first–computer last strategy can reduce the cost-to-target by half compared with only human designers. Finally, we highlight cultural challenges in partnering humans with computers that need to be addressed when introducing artificial intelligence in developing semiconductor processes.

Industrial TCAD: Modeling Atoms to Chips

The objective of this work is to briefly illustrate the breadth of problems industrial technology computer aided design (TCAD) departments are expected to address when supporting modern semiconductor process development, focusing on two important trends. The first is the incredible expansion of the simulation domain both downward to atomic dimensions and upward to the very large-scale die-level simulations needed for product design. The second trend is the continuing necessity of using computational efficient continuum approaches, fortified with more physically rigorous methods, to meet both accuracy and wall-clock time requirements of industrial process development. Both of these trends will be illustrated with applications work done at Intel.

Design of negative capacitance tunneling field effect transistor with dual-source U-shape channel, super-steep subthreshold swing and large on-state current

With the rapid development of semiconductor process, both tunneling field effect transistor (TFET) and negative capacitance field effect transistor (NCFET) are regarded as the effective low power devices. In this paper, a novel silicon-based dual source U-shaped channel TFET with negative capacitance (NCDU-TFET) is proposed and investigated by Synopsys Sentaurus TCAD. We pick ferroelectric material (Hf0.5Zr0.5O2) as the gate dielectric. The higher electric field caused by negative capacitance effectively increases the tunneling rate, so the super-steep subthreshold swing (SS) and higher on-state current are obtained for NCDU-TFET. Besides, the impacts of device parameters including gate dielectric layer thickness, coercive electric field and remnant polarization are also analyzed systematically in this paper. The simulation results indicate the average SS of NCDU-TFET is 17.04mV/dec, which is much lower than that of DU-TFET. And the on-state current of NCDU-TFET is nearly three orders of magnitude higher than that of DU-TFET. So NCDU-TFET has the potential to be used as a low-power component for large-scale integrated circuits.

Focus on lasers, imaging, and microscopy

Focus on lasers, imaging, and microscopy

How Much Will Gallium Oxide Power Electronics Cost?

Samantha Bench Reese is a senior engineer at the Strategic Energy Analysis Center at National Renewable Energy Laboratory (NREL). As an analyst, Samantha helps put early-stage research problems in context of technoeconomic tradeoffs and analytically shows technology potential through supply-chain analysis, trade-flow mapping, market research, and building bottom-up cost models. Prior to joining NREL, she helped transition products from R&D to volume manufacturing. Samantha's background is in mechanical and electrical engineering. She received an M.S. in Engineering and Applied Science from Yale University and a B.S. in Engineering and Applied Science from California Institute of Technology (Caltech). Timothy Remo is a manufacturing analyst in the Techno-Economic Analysis Group in the Strategic Energy Analysis Center at NREL. Tim’s areas of expertise include cost analysis of semiconductor manufacturing, process development and process optimization, and design of experiments. His research interests include cost-competitive renewable energy alternatives, economics of changing energy costs and demand, and challenges associated with smarter grid technology. Prior to joining NREL, Tim was a process and product engineer in the semiconductor and photovoltaics industry. Tim received his B.S. in Mechanical Engineering from University of South Florida and B.A. in Physics from University of Florida. Johney Green Jr. is an Associate Laboratory Director for Mechanical and Thermal Engineering Sciences (MTES) at NREL. He oversees NREL's transportation, buildings, wind, water, geothermal, advanced manufacturing, and concentrating solar power research programs. Prior to joining NREL, Johney held a number of leadership roles at Oak Ridge National Laboratory (ORNL), served as technical coordinator at the U.S. Department of Energy, and worked with Ford Motor Company. Green has received several awards during his career and served on numerous advisory boards. Dr. Green received his Mechanical Engineering degrees from Georgia Institute of Technology (Ph.D., M.S.) and The University of Memphis (B.S.). Andriy Zakutayev is a scientist at Materials Science Center at NREL, leading a team working on new materials for advanced energy technologies. His research interests include discovery and development of materials for solar cells, Li-ion batteries, fuel cells, power electronics, and other renewable energy technologies. Andriy is an author of more than 100 peer-reviewed publications and a reviewer for more than 50 scientific journals. He has received an EMRS Young Scientist Award along with many other professional recognitions. Dr. Zakutayev received his Ph.D. in Physics from Oregon State University and B.S. in Electronics from Lviv Polytechnic National University (Ukraine).

FEI Helios NanoLab 400S FIB-SEM

The FEI Helios NanoLab400S FIB-SEM is one of the world's most advanced DualBeamTM focused ion beam (FIB) platforms for transmission electron microscopy (TEM) sample preparation, scanning electron microscopy (SEM) imaging and analysis in semiconductor failure analysis, process development and process control. The FEI Helios NanoLab400S FIB-SEM combines an ElstarTM electron column for high-resolution and high-contrast imaging with a high-performance SidewinderM ion column for fast and precise cross sectioning. The FEI Helios NanoLab M 400S is optimised for high throughput high-resolution S/TEM sample preparation, SEM imaging and energy dispersive X-ray analysis. Its exclusive FlipStageTM and in situ STEM detector can flip from sample preparation to STEM imaging in seconds without breaking vacuum or exposing the sample to the environment. Platinum gas chemistry is the preferred metal deposition when a high deposition rate and precision of the deposition are required. Carbon deposition can be chosen as well. The system additionally allows for spatially resolved compositional analysis using the attached EDAX Genesis XM 4i X-ray microanalysis system.

Factors influencing filling degree in nanoimprint lithography with pseudoplastic fluid

As a novel development of semiconductor process, direct metallic patterning has the advantages of simple steps, low cost, etc. However, almost all transfer media are Newtonian fluids in traditional nanoimprint lithography. Newtonian fluid viscosity is constant. Too high a viscosity is adverse to filling the small space, and if viscosity is too low, it is harmful to solidify graphics. So an appropriate viscosity range that can both realize a high filling degree and benefit solidification is difficult to determine. Pseudoplastic fluid viscosity decreases with the increase of shear rate. The problem would be solved well when pseudoplastic fluid is used as a transfer medium. Synthesizing the advantages of direct metallic patterning and pseudoplastic fluid feature, a novel idea is put forward. The pseudoplastic metal nanofluids, which would be fabricated with metal nanoprticals, can take the place of transfer medium in nanoimprint lithography. Based on the finite element method, COMSOL software is used to compute the filling degree of pseudoplastic fluid, and the results are compared with those of Newtonian fluid under the same conditions. Factors, such as viscosity, imprinting speed, pressure, etc., which would affect filling degree, can be obtained from simulation results. These parameters provide a theoretical basis for designing technological process and fabricating pseudoplastic fluids in future work.

In-Situ Measurement of the Relative Thermal Contributions of Chemical Reactions and Ions During Plasma Etching

Plasma etch behavior is often explained in terms of "physical" and "chemical" components: both critically related to surface temperatures generated during plasma etching. In an attempt to measure the chemical etch rate component, a specially prepared, 300mm autonomous temperature sensor wafer was used to simultaneously record dynamic surface temperature during plasma etching of photo resist coated and bare silicon surfaces. Data for N2 / H2, Ar / O2, O2 and Cl2 etching chemistries were then compared with measured resist etch rates and RF sensor wafer data. Although insulation of the temperature sensors from the plasma by the 3 micron resist coating prevented calculation of the etch rate chemical component, the capability of this methodology with resist coatings < 500nm was shown. In addition the use of both RF and temperature sensor wafers to quickly identify and correct semiconductor etch process development issues related to isotropic etch non-uniformity was shown.

Adhesion of Crystalline GeSbTe/TiN Interface Characterized by Four Point Bend, Nanoindentation, and Nanoscratch

AbstractReversible structural phase change phenomenon of certain chalcogenide materials has been investigated extensively in the past decades. Among various phase change chalcogenide materials, Ge2Sb2Te5 (GST) is the most studied material due to its superior optical, electrical and mechanical properties. One of the challenges in using GST is the poor adhesion between crystalline GeSbTe (c-GST) and the substrate, such as TiN. In this work, the adhesion of the c-GST/TiN interface of two samples deposited by different techniques was characterized using four-point bend, nanoindentation and nanoscratch techniques. The nanoindentation and nanoscratch data agree well with the four point bend data. The paper also discusses the application potential of nanoindentation and nanoscratch techniques as qualitative methods for adhesion evaluation in semiconductor process development.

Electron Tomography and Three-Dimensional Aspects of Transmission Electron Microscopy

Abstract Transmission electron microscopy (TEM) plays an important role semiconductor process development, defect identification, yield improvement, and root-cause failure analysis. At the same time, however, certain artifacts of specimen preparation and imaging present barriers for linear scaling of TEM techniques. This article assesses these challenges and explains how electron tomography is being used to overcome them.

Yield learning and the sources of profitability in semiconductor manufacturing and process development

A numerical model that identifies the high-leverage variables associated with profitability in semiconductor manufacturing is presented. Varying the parameters of the model demonstrates that a rapid yield-learning rate determines profitability more than any other factor does. Factors such as ramping-up early, adding fab capacity, depressing the terminal fault density, and shrinking die size all yield diminishing returns. The model also suggests that developing a rapid problem-solving capability in the early stages of process development enables successful yield learning.

Foundry trends [IC manufacturing

The foundry business model of integrated circuit manufacturing involves focused development of semiconductor processes and manufacturing technology by foundries, to serve the needs of innovative IC designers who no longer wish to own some or even any of their own manufacturing facilities. It has created significant new opportunities for fabless semiconductor companies while opening new outsourcing opportunities for integrated device manufacturers.

Knowledge transfer and the limits to profitability: an empirical study of problem-solving practices in semiconductor manufacturing and process development

A broadly based empirical study of problem-solving practices in the semiconductor industry reveals that the inability to transfer knowledge rapidly is limiting the profitability of semiconductor, manufacturers. Extremely high user loss rates force users and suppliers of semiconductor process and diagnostic technology to solve problems as rapidly as possible. Unfortunately, both sides possess knowledge that is required to solve problems but cannot be transferred rapidly enough for extensive losses to be avoided. Collaboration between users and suppliers, in which problem solvers physically relocate from one side's site to the other's, is minimizing losses but creating a shortage of experts that threatens the health of the industry. A series of practices that will reduce the cost of knowledge transfer is presented. Foremost among these is the establishment of an Internet-enabled toolkit for remote diagnostics and repair.

Chemical Characterization of Semiconductor Defects and Particles on the Wafer Surface by Multiple Microanalysis Techniques

Abstract Development of future semiconductor processes and improving existing ones requires a strong capability to identify and eliminate the sources of particle defects. The current industry approach for accomplishing this task is to analyze the particles on the wafer surface. The most commonly used technique for this purpose is SEM with EDX (SEM/EDX). This approach provides information about defect chemistry and morphology, which in turn provides a direct path to the reevaluation of processes and hardware parts needed to determine the root cause of a problem. However, the SEM/EDX has three fundamental limitations: (a) it is a large volume technique and therefore, the sensitivity can be insufficient for sub micron particles and thin patches; (b) there is no chemical bonding information due to poor energy resolution; (c) charging problem for dielectrics. In some cases there is a need to use other techniques to support or substitute the EDX results.

Addressing environment, health, and safety in semiconductor process development

Motorola has traditionally focused on cost, yield, performance, and logistics as primary drivers for decision-making. In the semiconductor industry, environment, health, and safety (EHS) issues have resulted in major modifications of tools and process steps, as well as the addition of environmental controls to the facility, because they are not routinely considered when making process design and manufacturing choices, nor is their impact on cost, yield, and cycle time. Certain business driving forces, such as cost, sustainability of processes/tools, time to market, market access, and market share, are leading Motorola to a cultural change in which EHS impacts must be considered during product and process design; however, design and process engineers have not been able to adequately address these impacts. Motorola's Advanced Process Research and Development Laboratory (APRDL) in the Semiconductor Product Sector (SPS) has recognized this and has established its own environmental group (separate from the site EHS compliance group) to implement a design for EHS (DFEHS) strategy. The APRDL environmental group works with several project teams to address EHS issues in process development. These teams have been investigating copper metallization, wet cleans processes and tools, and other areas to ensure that the long-term EHS implications are identified and addressed before a process is transferred or a tool set recommended to a manufacturing fab. To empower engineers to consider, on their own, the EHS impacts of their materials and processes at the earliest possible stage, the APRDL environmental group has developed a DFEHS training course. This self-instructed, web-based course targets semiconductor design and process engineers and is available through Motorola University, the corporate training institution. The group has also established a procedure for approving new materials for the development lab in which EHS criteria are included.

Evaluation of an Auger electron spectrometer for 200 mm semiconductor defect review

Elemental and chemical microanalysis offered by Auger electron spectroscopy (AES) provides detailed elemental characterization of the typical films, particles and defects found in the ULSI regime. In this paper, an AES defect review tool (DRT) capable of accepting full 200 mm wafers is evaluated in a clean room installation to determine the performance and applicability of the tool to current in-line analytical needs of semiconductor manufacturing and process development. To meet these needs, an AES DRT must offer precise wafer positioning, maximum throughput and minimum contamination. The instrument under evaluation was a beta site installation of the first SMART 200 AES DRT manufactured by Physical Electronics (PHI). The vacuum components were designed to accept large samples on a 200 mm wafer-capable UHV stage manufactured by Raith GmbH (Germany). Based on this evaluation, it was found that the SMART 200 has the potential to handle moderate production volumes and become a valuable tool for timely defect analysis and process monitoring. © 1998 John Wiley & Sons, Ltd.

Material properties of low pressure chemical vapor deposited silicon nitride for modeling and calibrating the simulation of advanced isolation structures

The increasing cost and complexity of semiconductor process development has lead to the widespread use of multidimensional semiconductor process simulators. The success of a program like SUPREM−IV is primarily due to the fact that it is based on physical models, rather than empirical equations. This is in contrast to the first generation of process simulators, which calculated impurity profiles and oxide thickness in one dimension based on semiempirical approaches. SUPREM−IV incorporates two-dimensional coupled stress-dependent oxidation and impurity diffusion, which allows the accurate simulations of state-of-the-art integrated processes, provided that accurate model parameter sets are available. In this article we present an improved calibration methodology for simulation of advanced isolation technologies using SUPREM−IV, based on the experimental determination of the material properties of silicon nitride. The proposed strategy is applicable not only to SUPREM−IV but to any numerical simulator that uses the stress-dependent oxidation models to calculate oxide growth. In order to simulate experimental isolation boundary shapes, the oxidation models in SUPREM−IV must be calibrated. This requires a set of five fitting parameters, i.e., the material viscosities and activation volumes for stress-dependent diffusion, reaction rate, and critical stress. These parameters form a quintuplet but are not unique. Multiplying the viscosity values and dividing the activation volumes by a constant will yield exactly the same isolation structure boundary shape. The calculated stresses in the substrate however do not remain constant when different quintuplets are used. This has serious implications since isolation structures require the stress levels in the silicon substrate to remain well below the yield stress of silicon. If a nonoptimal parameter set is used, incorrect designs will result. Based on the experimental extraction of the silicon nitride viscosity by measuring the relative film thickness shrinkage rate as a function of temperature, a scaled parameter set has been derived. SUPREM−IV simulations predict identical boundary shapes but the simulated stress levels are different from the values obtained using the default parameter set. In order to validate the stress simulations, a comparison with experimental stress values measured by micro-Raman spectroscopy has been carried out. It has been found that the quintuplet based on the experimental nitride viscosity values yields the best agreement with the experimental stress data, supporting the accuracy of the new model parameter set.

Applications of focused ions beams to nondestructive analyses

Nondestructive analysis with focused ion beams (FIBs) has considerable advantages over conventional ion beam or destructive FIB analyses. It meets the requirement by the state-of-the-art semiconductor process development. Two or three dimensional analyses on ion implanted micro structures are possible when is combined with Rutherford backscattering. Soft error immunity in memory chips can be evaluated by a new method using a focused ion beam. Recent applications of nondestructive analysis using FIBs to ion implantation related processes are discussed.