Semiconductor Manufacturing Industry Research Articles

Application of the adverse outcome pathway framework to predict the toxicity of chemicals in the semiconductor manufacturing industry.

BackgroundTo solve current issues using big data, solve current issues related to the semiconductor and electronics industry, I tried to establish the data for each toxicity mechanism for adverse outcome pathway (AOP) for the exposure.ObjectiveI planned to increase the efficiency of human hazard assessment by searching, analyzing, and linking test data on the relationship between key events occurred at each level, which are the biological targets of chemicals in semiconductor manufacturing.ResultsIt was found that 48 kinds of chemicals had 11 AOPs, while 103 chemicals had multiple AOPs, and 26 had case evidence. As a result of AOP analysis, it was found that a total of 320 chemicals had 42 AOPs, and 190 major chemicals corresponded to 11 AOPs. It was found necessary to develop a complex AOP and secure an (inhalation or dermal) exposure scenario for combined exposure at work. As a comparative search (41 out of 190 chemicals) of biomarkers specific to occupational diseases, 12 biomarkers were found to be related to breast cancer. The AOPs for 50 specific chemicals were presented, together with occupational disease-specific AOPs and key events relationship from 50 chemicals, and taxonomic classification for each AOP analysis could be found. With a comparative search, 41 out of 190 chemicals were associated with specific biomarkers for occupational diseases, and 12 mRNA or protein biomarkers were found to be related to breast cancer by cross-validation with the attached Table 24 of the Enforcement Regulations of the OSHAct and the CTD.ConclusionThe mechanism of occupational diseases caused by chemicals was presented, together with pathological preventions. I believe that a strategy is needed to expand the target organization for each chemical by linking with activities, such as work environment measurement, and cooperating with screening items and methods suitable for toxic chemicals, like AOP tools.Supplementary InformationThe online version contains supplementary material available at 10.1007/s13273-021-00139-4.

Fault recognition based test score for improving the accuracy of defect diagnosis

Diagnosis is an essential step to improve the yield in semiconductor manufacturing industry. It is performed on a failing chip to determine the location of defects. However, the defect diagnosis procedure may obtain too much candidate faults which lead to difficulties in next physical failure analysis. Recently, the methods based on test score to reduce candidate fault set are proved to be effective. The previous test score diagnosis method based on fault free information computes a score for each test which implies the fault identification ability. This letter proposes a novel fault recognition based test score for diagnosis which considers the fault identification capability of tests more comprehensively to improve the original method. More information provided by unique responses and faults detected of a test is added to evaluate the fault recognition for calculating a test score. Then the novel test score which takes more advantages of diagnostic information is applied to adjusting the fault score and reducing the candidate set. The experimental results show that the novel approach reaches smaller fault candidate set than the previous method and increases the diagnostic resolution and precision, and thus provides an effective improvement on the accuracy of diagnosis.

Features and Structure of Diaphragm Type Vacuum Pump

The diaphragm type vacuum pump is a vacuum pump that exhausts gas using the reciprocating motion of the diaphragm. Especially, it is not contaminated by oil vapor. This pump is ideal for applications that require a clean atmosphere. With the recent rapid development of the semiconductor manufacturing industry and the electronics equipment industry, demand for the diaphragm type vacuum pump has also been increasing.

Wafer Delay Analysis and Workload Balancing of Parallel Chambers for Dual-Armed Cluster Tools With Multiple Wafer Types

We examine a scheduling problem for a dual-armed cluster tool that processes multiple similar wafer types concurrently. It has been recently proved that the well-known swap sequence, which is widely used for single wafer type processing, also minimizes the cycle time for concurrent processing. In this article, we wish to minimize wafer delays in a process chamber, which are critical to wafer quality degradation, while maintaining the minimum cycle time. In particular, we show that concurrent processing of wafers with different processing times complicates the analysis of wafer delays significantly, and the wafer delays can be remarkably reduced by finding a proper cycle plan which is the release sequence of different wafer types. We first characterize wafer delays for a given cycle plan by analyzing the circuits of the timed event graph (TEG) model. From this, we prove that concurrent processing of wafers may cause a significant workload imbalance between parallel chambers of a process step, and hence the wafer delays increase substantially. We present that the wafer delays are minimized by a cycle plan that evenly balances workloads between parallel chambers. We also propose how wafer loading task at each process step has to be postponed to meet wafer delay constraints while maintaining the minimum cycle time. Note to Practitioners —Wafer quality control has become an essential fab operational problem in semiconductor manufacturing industry. In cluster tools, which are dominantly being used for diverse wafer fabrication stages, it has been proven that the wafer delays within process chambers have a crucial impact on the wafer quality. Accordingly, modern fabs have introduced stringent quality control to regulate wafer delays in cluster tools. In this research, we propose a scheduling strategy to minimize the wafer delays when a cluster tool concurrently processes multiple wafer types. We first show that the release sequence of different wafer types significantly impacts the wafer delays under concurrent processing, and we then propose how these wafer delays can be minimized by finding the optimal wafer release sequence.

Smart Manufacturing Application in 3D FinFETs: New Approach for Performance-Yield Co-Optimization Based on Virtual Process Integration.

Currently, the semiconductor manufacturing industry is seeing rapid movement from 2D planar to 3D FinFET technology. Among SCE-enhanced scaled fin structures, depending on stress engineering to increase mobility, merged elevated source-drain (eSD) epi structures are widely used because they can maximize device performance by reducing Rsd. While there is active research on device and epi own defects related to eSD process, there is no study on yield effect. Smart manufacturing (SM) applications, which form the core of Industry 4.0, are difficult to find in bulk-FinFETs, and it is difficult to find hidden systematic defects of complex three-dimensional structures using limited analyses such as in-line monitoring and abnormal trend detection. In this study, we investigate the root-cause of gate to eSD short, which is the primary FinFET yield detractor, and we obtain an optimized solution to improve yield by 25.2% without performance degradation. These improvements are accomplished using our in-house SM platform that consists of four components: a virtual integration (VI) module for defining defects such as physical connection, void, and not open; a hot spot module for identifying the location of needed process control; an advanced analytics module including algorithms for selecting key features and predicting the fail bit; and an optimizer module that can co-optimize yield and performance.

Research on Classification and Application of Comprehensive Energy Load of Important Users

Important load users are the lifeline of urban development, and their energy security system is not yet complete. According to the existing power load classification guarantee principle, the comprehensive energy load classification and guarantee measures of important users are discussed. At the same time, it analyzes the characteristics of existing security resources, selects the semiconductor manufacturing industry as the application scenario, and explores more possibilities for flexible configuration of security resources for users with important loads. Finally, the distributed energy system is proposed as a security resource for semiconductor companies, and it is used as a backup with the mains, replacing conventional diesel generating sets, and switching from cold standby to hot standby. This will reduce the initial investment in enterprise construction, improve the utilization of security resources, and the reliability of energy supply for important load users.

Process Induced Stress Optimization for Compressively Stressed p-Channel FinFET at 7N

At 7nm technology node, the trigate FinFETs are the promising candidates for modern integrated circuits. Their optimal design and improved performance are key demands for most of the leading semiconductor manufacturing industries. This work proposes an improvement of electrical performance through process induced stress optimization for a compressively stressed FinFET at a 7nm Technology node. The variation of two design parameters (fin angle and epi angle) can lead to a change in stress and hence the devices’ electrical performance, which is the major focus of this study. A process induced compressively stressed p-channel FinFET at 7nm Technology node is virtually fabricated using Technology CAD (TCAD) by introducing a SiGe epitaxial layer at Source and Drain regions. The variation of electrical performances with change in epi angle (θEpi) and fin angle (θFin) is critically analyzed. These results predict the improvement of the drive current and reduction in short channel effect with the appropriate selection of the θFin and θEpi. Hence, the predictive TCAD simulations explored the new avenues of strain-engineered FinFET for future CMOS technology generations.

Remote GaN metalens applied to white light-emitting diodes.

In this work, a gallium nitride (GaN) metalens as a remote device has been applied to a commercially available white light-emitting diode (LED). We show the successful demonstration in fabricating the high-aspect-ratio GaN metalens capable of diffraction-limited focusing with an experimentally focusing efficiency up to 89% at the wavelength of 450 nm. The metalens can also resolve the subwavelength features as imaging. For the proof of concept, the rainbow-like phenomenon can be observed by using the remote GaN metalens to disperse the white light radiated by the white LED. The diode lasers working at various wavelengths have been employed to carefully verify the positions of colors in the rainbow-like profile. The results in this study can inspire the semiconductor manufacturing industry at integrating metalenses of various kinds and functionalities into the package of LED modules in the near future and prospect widespread applications in advanced solid-state lighting.

Self-Supervised Representation Learning for Wafer Bin Map Defect Pattern Classification

Automatic identification of defect patterns in wafer bin maps (WBMs) stands as a challenging problem for the semiconductor manufacturing industry. Deep convolutional neural networks have recently shown decent progress in learning spatial patterns in WBMs, but only at the expense of explicit manual supervision. Unfortunately, a clean set of labeled WBM samples is often limited in both size and quality, especially during rapid process development or early production stages. In this study, we propose a self-supervised learning framework that makes the most out of unlabeled data to learn beforehand rich visual representations for data-efficient WBM defect pattern classification. After self-supervised pre-training based on noise-contrastive estimation, the network is fine-tuned on the available labeled data to classify WBM defect patterns. We argue that self-supervised pre-training with a vast amount of unlabeled data substantially improves classification performance when labels are scarce. We demonstrate the effectiveness of our work on a real-world public WBM dataset, WM-811K. The code is available at https://github.com/hgkahng/WaPIRL.

A simheuristic approach for the flexible job shop scheduling problem with stochastic processing times

In this work, we address the flexible job shop scheduling problem (FJSSP), which is a classification of the well-known job shop scheduling problem. This problem can be encountered in real-life applications such as automobile assembly, aeronautical, textile, and semiconductor manufacturing industries. To represent inherent uncertainties in the production process, we consider stochastic flexible job shop scheduling problem (SFJSSP) with operation processing times represented by random variables following a known probability distribution. To solve this stochastic combinatorial optimization problem we propose a simulation-optimization approach to minimize the expected makespan. Our approach employs Monte Carlo simulation integrated into a Jaya algorithm framework. Due to the unavailability of standard benchmark instances in SFJSSP, our algorithm is evaluated on an extensive set of well-known FJSSP benchmark instances that are extended to SFJSSP instances. Computational results demonstrate the performance of the algorithm at different variability levels through the use of reliability-based methods.

A self-organized approach for scheduling semiconductor manufacturing systems

In semiconductor manufacturing industry, traditional scheduling rules are not conducive to improving production capacity to autonomously adjust based on real-time status. To fill this gap, this study proposes a dynamic dispatching rule based on self-organization (DDRSO) to autogenerate optimal scheduling scheme through mechanisms of interaction, coordination and competition. Besides, an extended DDRSO is proposed to further consider hot lots and transient dynamic bottlenecks. Both DDRSO and E-DDRSO are designed from three aspects: role definition of self-organization units, negotiation mechanism among self-organization units, and decision methods. This research adopts a benchmark industrial manufacturing system to illustrate the availability of the proposed approach. Compared with heuristic dispatching strategies, DDRSO achieves improvement on MOV, TH and ODR by 4.9%, 9.06% and 20.23%, respectively. Meanwhile, E-DDRSO performs better than DDRSO under all workload levels. In addition, compared with a flexible dispatching method BPSO-SVM, E-DDRSO also obtain better performances, especially improvement on CT by 16.51%.

Contextual Anomaly Detection in Solder Paste Inspection with Multi-Task Learning

In this article, we study solder paste inspection (SPI), an important stage that is used in the semiconductor manufacturing industry, where abnormal boards should be detected. A highly accurate SPI can substantially reduce human expert involvement, as well as reduce the waste in disposing of the boards in good condition. A key difference today is that because of increasing demand in board customization, the number of board types increases substantially and quantity of the boards produced in each type decreases. Thus, the previous approaches where a fine-tuned model is developed for each board type are no longer viable. Intrinsically, our problem is an anomaly detection problem. A major specialty in today’s SPI is that the target tasks for prediction cannot be fully pre-determined due to context changes during the solder paste printing stage. Our experiences show that a conventional approach to first define a set of tasks and train these tasks offline will lead to low accuracy. Here, we propose a novel multi-task approach, where the performance of all target tasks is ensured simultaneously. We note that the SPI process is streamlined and automatic, allowing the SPI time for only a few seconds. We propose a fast clustering algorithm that reuses existing models to avoid retraining and fine tune in the inference phase. We evaluate our approach using 3-month data collected from production lines. We show that we can reduce 81.28% of false alarms. This can translate to annual savings of $11.3 million.

Ball Misplace Mitigation through Process Optimization of Advanced Leadframe Package

One of the challenging assembly processes in semiconductor manufacturing industry is stencil printing using solder paste as direct material. With this technology, some issues were encountered during the development phase of an advanced leadframe device and one of which is the solder ball misplace or off-centered ball. This paper, hence, focused on addressing the ball misplace issue at stencil printing process. Comprehensive parameter optimization particularly on the print speed and print force was employed to eliminate or significantly reduce the ball misplace defect at stencil printing process. With this process optimization and improvement, a reduction of around 96 percent ball misplace occurrence was achieved.

Using product data management technology to semiconductor manufacturing industry

Many enterprises cannot cost down and quality improve. So, speeding up production time is a new competition ability. Most Product Data Management (PDM) can automate to input files and data through known procedures. But some technology cannot satisfy the requirement for production information in precision, clearness and customization. This paper proposed a technique using application product data management on Integrated Circuit (IC) Design. Using internet, network and circuit simulation for solution problems, resulting from R&D process and the compatibility of customer required products. Using the proposed model in PDM to reduce the correction rate after the IC design and production in order to satisfy customers’ demands. The results of this paper are the participating teams of strategic alliance can develop IC product to integrate enterprise subject to the related product quality. Support correct information of product for customer demands to develop relative products. Through the function of IC circuit simulation. The proposed model can verify customers’ product instantly to reduce time and cost, and to increase the design efficiency and quality. The customer can use ICs products from building up IC courses. Using this technology can forecast customers’ demands, development business trend and strengthen communicate with customers to build customer relationship, put IC products into the commercial market more quickly and enhance customer competition ability. Therefore, for ICs designer can get better product quality, shorten product R&D time and strengthen the competition ability.

Guest Editorial Special Section on the 2019 SEMI Advanced Semiconductor Manufacturing Conference

Dear readers—We hope this editorial finds you and your family safe as we and the world battle—or, hopefully at the time of this publication, recover from—perhaps the greatest world-wide health crisis in the last century, COVID-19. Fortunately, the contributions of our semiconductor manufacturing industry over the last 40 years have put us in a much more comfortable position than those who faced past pandemics. It is likely that many of you have been working from home using your high-speed Internet connection and one of multiple computers that you and most families own. The worldwide Internet and computing infrastructure that our industry has enabled allows many engineers and others to VPN into work, communicate and share documents via e-mail, and attend video meetings. On the personal side, you can keep up with family and friends, with the latest news, and information and instructions from the government. Semiconductors allow your children to attend (or perhaps teach) school remotely. Certainly school aged children will be missing contact with their friends, but, fortunately, they can still video chat, message, or at least call friends with their mobile phones. The whole family can enjoy their favorite shows and movies via streaming services, and of course try new video games.

Performance and improvement of cleanroom environment control system related to cold-heat offset in clean semiconductor fabs

Clean room is a key technology to guarantee the normal operation in semiconductor manufacturing industry. On-site measurement of indoor environment and performances of the air conditioning systems in four clean semiconductor fabs have been conducted in summer in this study. It’s indicated that indoor environment of these four fabs all meet the requirement and a satisfied control accuracy is achieved. The main energy-consuming facilities in the air conditioning system arises from the fan of air handling processors and chillers, which consumes about 80%–90% of the total. Reheating in make-up air handing process (MAU) occurs in the current system, resulting in cold-heat offset and extra energy loss. System schematic avoiding reheating based on the measured results is proposed. The proposed system where only part of indoor return air is cooled by the dry cooling coil (DCC) and achieves secondary return air could avoid the cold-heat offset. At full load condition, cooling supplies for DCC (QDCC) in the proposed system is about 40%–52% lower than that in the current system of these four fabs. No reheating exists in the proposed system, and QRH is saved 151–236 W/m2. The research helps to reveal the operating performance and propose appropriate improving approaches for these circumstances.

Advanced Semiconductor Design through Specialized Printable Conductive Layer

Semiconductor package miniaturization and thinning have become of particular interest among semiconductor manufacturing industries, with each manufacturing company having specific approach and technical directions in providing unique solutions in their products. The paper provides a specialized design of manufacturing flow for semiconductor device through advanced fabrication method using stencil printing. The advanced process would significantly reduce the carrier thickness for the overall package height configuration of the device. The implementation of the specialized design and process would mitigate common assembly barriers and defects related in producing thin devices, hence, enabling cost-saving realization and manufacturing solution to package thinning and miniaturization with multiple input/output (I/O) requirements.

Outliers Detection Models in Shewhart Control Charts; an Application in Photolithography: A Semiconductor Manufacturing Industry

Shewhart control charts with estimated control limits are widely used in practice. However, the estimated control limits are often affected by phase-I estimation errors. These estimation errors arise due to variation in the practitioner’s choice of sample size as well as the presence of outlying errors in phase-I. The unnecessary variation, due to outlying errors, disturbs the control limits implying a less efficient control chart in phase-II. In this study, we propose models based on Tukey and median absolute deviation outlier detectors for detecting the errors in phase-I. These two outlier detection models are as efficient and robust as they are distribution free. Using the Monte-Carlo simulation method, we study the estimation effect via the proposed outlier detection models on the Shewhart chart in the normal as well as non-normal environments. The performance evaluation is done through studying the run length properties namely average run length and standard deviation run length. The findings of the study show that the proposed design structures are more stable in the presence of outlier detectors and require less phase-I observation to stabilize the run-length properties. Finally, we implement the findings of the current study in the semiconductor manufacturing industry, where a real dataset is extracted from a photolithography process.

Chemical Use and Associated Health Concerns in the Semiconductor Manufacturing Industry

BackgroundResearch on the status of many chemicals used in the semiconductor industry is needed. The purpose of this study was to describe the overall status of chemical use in the semiconductor industry in Korea and to examine it from a health perspective.MethodsData on the status of chemical use and safety data sheets at 11 of 12 major semiconductor workplaces in Korea were collected. The number of chemical products and chemical constituents, quantities of chemicals, and trade secret ingredients used, as well as the health hazards were examined.ResultsOn average, 210 chemical products and 135 chemical constituents were used at the surveyed workplaces. Among all chemical products, 33% (range: 16–56%) contained at least one trade secret ingredient. Most of the trade secret ingredients were used in the photolithography process. Several carcinogens, including sulfuric acid, chromic acid, ethylene oxide, crystalline silica, potassium dichromate, and formaldehyde were also used. Only 29% (39 of 135) of the chemical constituents had occupational exposure limits, and more than 60% had no National Fire Protection Association health, safety, and reactivity ratings. Based on the aforementioned results, this study revealed the following. First, many chemical products and constituents are being used in the semiconductor industry and many products contained trade secret ingredients. Second, many products contained significant amounts of carcinogenic, mutagenic, and reproductive toxicant materials.ConclusionWe conclude that protecting workers in the semiconductor industry against harm from chemical substances will be difficult, due to widespread use of trade secret ingredients and a lack of hazard information. The findings of the status of chemical use and the health and safety risks in semiconductor industry will contribute to epidemiological studies, safe workplace, and worker health protection.

Automatic Reclaimed Wafer Classification Using Deep Learning Neural Networks

Silicon wafer is the most crucial material in the semiconductor manufacturing industry. Owing to limited resources, the reclamation of monitor and dummy wafers for reuse can dramatically lower the cost, and become a competitive edge in this industry. However, defects such as void, scratches, particles, and contamination are found on the surfaces of the reclaimed wafers. Most of the reclaimed wafers with the asymmetric distribution of the defects, known as the “good (G)” reclaimed wafers, can be re-polished if their defects are not irreversible and if their thicknesses are sufficient for re-polishing. Currently, the “no good (NG)” reclaimed wafers must be first screened by experienced human inspectors to determine their re-usability through defect mapping. This screening task is tedious, time-consuming, and unreliable. This study presents a deep-learning-based reclaimed wafers defect classification approach. Three neural networks, multilayer perceptron (MLP), convolutional neural network (CNN) and Residual Network (ResNet), are adopted and compared for classification. These networks analyze the pattern of defect mapping and determine not only the reclaimed wafers are suitable for re-polishing but also where the defect categories belong. The open source TensorFlow library was used to train the MLP, CNN, and ResNet networks using collected wafer images as input data. Based on the experimental results, we found that the system applying CNN networks with a proper design of kernels and structures gave fast and superior performance in identifying defective wafers owing to its deep learning capability, and the ResNet averagely exhibited excellent accuracy, while the large-scale MLP networks also acquired good results with proper network structures.