Abstract
Currently, the semiconductor manufacturing industry is seeing rapid movement from 2D planar to 3D FinFET technology. Among SCE-enhanced scaled fin structures, depending on stress engineering to increase mobility, merged elevated source-drain (eSD) epi structures are widely used because they can maximize device performance by reducing Rsd. While there is active research on device and epi own defects related to eSD process, there is no study on yield effect. Smart manufacturing (SM) applications, which form the core of Industry 4.0, are difficult to find in bulk-FinFETs, and it is difficult to find hidden systematic defects of complex three-dimensional structures using limited analyses such as in-line monitoring and abnormal trend detection. In this study, we investigate the root-cause of gate to eSD short, which is the primary FinFET yield detractor, and we obtain an optimized solution to improve yield by 25.2% without performance degradation. These improvements are accomplished using our in-house SM platform that consists of four components: a virtual integration (VI) module for defining defects such as physical connection, void, and not open; a hot spot module for identifying the location of needed process control; an advanced analytics module including algorithms for selecting key features and predicting the fail bit; and an optimizer module that can co-optimize yield and performance.
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