Semiconductor Manufacturing Company Research Articles

Redefining Monitoring Rules for Intelligent Fault Detection and Classification via CNN Transfer Learning for Smart Manufacturing

Fault detection and classification has been employed to enhance yield and product quality for smart semiconductor manufacturing. For early detection of abnormal events that cause defects, the status variables identification data collected by the sensors embedded in advanced machines can be analyzed to derive the actions for advanced process control and advanced equipment control. However, the validity and effectiveness of fault detection and classification technologies may highly depend on domain knowledge and experience of the process engineers who should redefine the monitoring rules quickly when new process excursion occurred especially when ramping up new technologies and products. Motivated by realistic needs, this study aims to propose a novel strategy to empower intelligent fault detection and classification that employed convolutional neural network to analyze the feature SVID data and determine the conditions of the wafers, while shorten the cycle time for self-learning from domain knowledge and redefining new monitoring rules for fault classification in real time. This approach is validated with an empirical study in a leading semiconductor manufacturing company in Taiwan. The results have demonstrated the practical viability of the developed solution.

A 0.4-V High-Gain Low-Noise Amplifier Using a Variable-Frequency Image-Rejection Technology

A 0.4-V high-gain low-noise amplifier (LNA) using a variable-frequency image-rejection technology in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process has been proposed. By using forward body biasing and folded topology, the supply voltage and power consumption can be reduced. For achieving low power consumption and small chip area, a feedback capacitor is used to shrink the size of the inductors of the input impedance matching. Moreover, a gain-enhancement-and-image-rejection (GEIR) circuit including an inductor and a variable capacitor is proposed for achieving GEIR simultaneously. The image-rejection frequency can be altered for avoiding strong image signals by the variable capacitor. The proposed LNA shows the measured results including a 15-dB power gain, a 2.6-dB noise figure, and a &#x2212;13-dBm input third-order intercept point at 2.4 GHz, respectively. And the measured variable image rejection ratio ranges from 14 to 39 dBc around 3&#x2013;3.6 GHz for avoiding strong image signals. The measured <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}} $ </tex-math></inline-formula> is 0.8 mW.

Hardware architecture of a digital piecewise linear chaotic map with perturbation for pseudorandom number generation

Piecewise linear chaotic map (PWLCM) is a simple chaotic system popularly used for generating pseudorandom numbers (PRN). Digital implementation of PWLCM degrades the randomness of the pseudorandom number due to the finite precision effect. The current paper presents a digital 1-dimensional PWLCM that mitigates the degradation of digital chaos by cascading the chaotic map with a three-stage XORed shift register that perturbs the output of the PWLCM. We further perturb the output of the shift register using a one-stage XOR post-processing. We also present the hardware architecture of the proposed system to generate a high throughput PRN sequence. The designed architecture is synthesized on Xilinx Zynq 7000 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) using TSMC (Taiwan Semiconductor Manufacturing Company) 90 nm CMOS technology. We experimentally validate the randomness of the output sequence using NIST test suite 800–22. In addition, we also perform security analyses such as phase space, key sensitivity, correlation, and information entropy. The statistical and security analysis confirms the efficiency of the proposed design in terms of randomness. The synthesis result demonstrates the achieved throughput as 1.296 Gbps at 81 MHz operating frequency on Zynq 7000 FPGA, whereas a throughput of 1.696 Gbps at 106 MHz operating frequency is achieved on ASIC.

A new high speed charge and high efficiency Li-Ion battery charger interface using pulse control technique

A new Li-Ion battery charger interface (BCI) using pulse control (PC) technique is designed and analyzed in this paper. Thanks to the use of PC technique, the main standards of the Li-Ion battery charger, i.e. fast charge, small surface area and high efficiency, are achieved. The proposed charger achieves full charge in forty-one minutes passing by the constant current (CC) charging mode which also included the start-up and the constant voltage mode (CV) charging mode. It designed, simulated and layouted which occupies a small size area 0.1 mm2 by using Taiwan Semiconductor Manufacturing Company 180 nm complementary metal oxide semi-conductor technology (TSMC 180 nm CMOS) technology in Cadence Virtuoso software. The battery voltage VBAT varies between 2.9 V to 4.35 V and the maximum battery current IBAT is 2.1 A in CC charging mode, according to a maximum input voltage VIN equal 5 V. The maximum charging efficiency reaches 98%.

Third order inverse multifunction filter employing MOS resistors and capacitors

AbstractThis paper presents a systematic approach for the realization of multifunction filter that includes third order inverse low pass filter (ILPF), band pass filter (IBPF), and high pass filter (IHPF) using two Operational Transresistance Amplifiers (OTRAs), MOS resistors, and few number of capacitors. An operational activity of inverse filter configuration (IFC) can be easily realized by proper selection of switches. In ideal case, third order of the filter characterizes a total roll‐off of 60 dB/decade but the proposed design offers a roll‐off in the range of 48.09 dB/decade to 57.74 dB/decade which may arises due to passive component tolerance and some design parameters. The proposed design brings an improvement in roll‐off around 20%–44% in comparison to existing literatures. The multifunction filter frequency response (ILPF, IBPF, and IHPF) is observed by using PSPICE simulation in which the core of the filter “OTRA” is integrated with 180 nm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology parameter. In addition to simulation results, hardware implementation of the proposed filter configuration validates the theoretical aspect of filter design.

A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding

Computing-in-memory (CIM) architectures have paved the way for energy-efficient artificial intelligence (AI) systems while outperforming von Neumann architectures. In particular, resistive RAM (RRAM)-based CIM has drawn attention due to high cell density, non-volatility, and compatibility with a CMOS process. RRAM also exhibits the feasibility of high-capacity CIM with multi-bit encoding per cell exploiting an appropriate ON/OFF resistance ratio. However, the prior work regarding multi-level RRAM cells mainly focused on achieving higher bit resolution in write without consideration of CIM performance. Thus, the circuit solution to achieve multi-bit encoding per cell dedicated to RRAM-based CIM (RCIM) is of importance to support high-capacity AI systems with reliable CIM performance. This article presents a 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 256 CIM multi-level RRAM macro featuring iterative write with verification to achieve reliable multi-bit encoding per cell and the voltage-sensing readout circuit to surmount the underlying logic ambiguity in RCIM architectures. In addition, we also demonstrate the key design space of a fabricated RRAM array in the write operation with extensive experiments. The test chip fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm CMOS and RRAM process achieves a peak energy efficiency of 118.44 TOPS/W in the ternary-weight multiply-and-accumulate (MAC) operation and demonstrates the feasibility of multi-level RCIM with voltage-sensing RCIM.

A Dual-Mode W-Band Eight-Way Parallel–Series Power-Combining PA With +18-dBm P sat and 15.1% PAE in 65-nm CMOS Technology

This letter presents the design of a Dual-mode W-band eight-way power-combining power amplifier (PA) implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology ( $f_{t}$ / $f_{{max}}$ : 210 GHz/240 GHz). A configurable parallel-series-based eight-way power combine technique is proposed to achieve high output power with high power efficiency near half of $f_{t}$ . The eight-way power-combiner is consisted of two transformer-based parallel two-way differential combiners and a coupled-line-based series combiner to achieve high passive efficiency and compact layout. The proposed PA achieves a measured peak gain of 30.9 dB with a bandwidth (BW) of 7.5 GHz. The PA has $P_{{sat}}$ of +18 dBm with an 1dB output compression point (OP1dB) of +13.8 dBm and a peak PAE of 15.1% in high-power mode. In the low-power mode (LPM), the measured $P_{{sat}}$ , OP1dB, and peak PAE are +13.6, +9.1 dBm, and 10.3%, respectively. The PAE is enhanced by 3.4% points at a 6-dB back-off in LPM. The core area of the proposed PA is 0.3 mm².

An Improved XGBoost Prediction Model for Multi-Batch Wafer Yield in Semiconductor Manufacturing

Wafer yield is one of the most critical indicators of product quality in semiconductor manufacturing companies. An accurate prediction can reduce the subsequent inspection process, improve production efficiency and reduce product scrap. However, existing end-to-end data-driven wafer yield prediction methods ignore the batch nature of the wafer production process, resulting in poor generalization of the prediction model in different batch wafers. Therefore, an improved XGBoost-based multi-batch wafer yield prediction model is proposed to address this problem. A multi-task learning mechanism is designed to realize the extraction of batch features, and a fusion training mechanism is established to realize the prediction output. Finally, the effectiveness of the prediction method is verified by experimental data collected from the real wafer fabrication process.

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872)10 to + (7.96872)10. The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as “block enabling” and “clock gating” are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

Chua's Oscillator With OTA Based Memcapacitor Emulator

A charge-controlled memcapacitor emulator design based on the current-mode technique has been proposed in this research work. The physical realization of a memcapacitor is an open problem that motivates creating newer designs for memcapacitor emulator circuits. The memcapacitor emulator comprises an operational transconductance amplifier (OTA), an active component and has additional passive elements. Memcapacitor, abstracted to have a (pinched) hysteresis loop, is emulated in this work, can be also observed as a nonlinear capacitor with memory in its physical form. The simulations are carried out using 0.18 μm (Taiwan Semiconductor Manufacturing Company) TSMC technology and a ±1.2 V supply voltage to analyse robustness of design through process corner, temperature variation, and non-volatility. Experimental validations are performed using ICs CA3080 on breadboard. An application of chaotic oscillator and adaptive learning circuit using a memcapacitor emulator circuit is shown as a practical case study.

Electronically Tunable Flux-Controlled Resistorless Memristor Emulator

This article demonstrates a voltage differencing inverting buffered amplifier (VDIBA)-based resistorless flux-controlled memristor emulator circuit with tunability. Two VDIBA blocks serve as active components, and a grounded capacitor serving as a passive part. The proposed emulator design is devoid of multipliers and resistors through effective utilization of port relationships. Including tunability, the suggested emulator functions in both incremental and decremental modes. It accurately depicts the attributes of an ideal memristor up to 12.7 MHz and consumes a total power of 1.34 mW. The mathematical analysis is substantiated through Cadence simulation in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m Taiwan Semiconductor Manufacturing Company (TSMC) technology with the supply voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 1 V. Nonideal, single/parallel, Monte-Carlo sampling and corner analysis were conducted to confirm circuit resilience. The nonvolatile nature of the presented emulator model has also been included. A breadboard prototype incorporating the ICs CA3080 and LT1193 are built to conduct an experimental demonstration. The experimental findings were consistent with the theoretical expectations and simulation results.

An EGFET Based Common Source Amplifier as a Low-Frequency Instrumentation Amplifier for Sensitivity Measurement on RuO2 Lactic Acid Biosensor

In this study, a low-frequency instrumentation amplifier (LFIA) integrated with an extended-gate field-effect transistor (EGFET) is presented to realize the simplicity common source amplifier (CSA) structure. The proposed EGFET CSA was developed by the 0.18-&#x03BC;m CMOS process technology of Taiwan Semiconductor Manufacturing Company (TSMC). The EGFET CSA has low frequency and noise immunity function, and it can effectively output the response signal, with good stability and effectively improve the sensitivity, not susceptible to environmental factors, easy to replace, and low cost. Moreover, the simple circuit design of the EGFET CSA was used to analyze the sensing characteristics and to improve the stability of the ruthenium dioxide (RuO₂) lactic acid (LA) biosensor. Therefore, the EGFET CSA is suitable for LA detection. The simple process of the EGFET CSA was used to analyze the sensing characteristics and to improve the stability of the ruthenium dioxide (RuO₂) lactic acid (LA) biosensor. An arrayed potentiometric LA biosensor based on the RuO₂ thin film was proposed and manufactured in this study. The experimental results indicated that the EGFET CSA as a low-frequency instrumentation amplifier has achieved a good sensitivity (53.41mV/mM) and satisfactory linearity (0.997) on the RuO₂ LA biosensor as compared with the V-T measurement system.

Similarity Search on Wafer Bin Map Through Nonparametric and Hierarchical Clustering

Searching for and comparing similar wafer maps can provide crucial information for root cause analysis in the manufacturing process of integrated circuits. Owing to the high dimensionality and complexity of defect patterns, comparison of similar maps in their entirety is inefficient. This paper proposes an automated similarity ranking system with a novel feature set as a reduced representation of wafer maps. To detect systematic failure patterns across wafer maps, we use nonparametric Bayesian clustering based on the Dirichlet process Gaussian mixture model, and hierarchical clustering based on the symmetric Kullback–Leibler divergence. The proposed features are efficient because they require minimal computation and storage; furthermore, they allow for highly discriminative rankings of similar failure patterns. Thus they are suitable for large-scale analysis of wafer maps. The proposed method is experimentally verified using a real wafer map dataset from a semiconductor manufacturing company, and a subset of WM-811K.

Agent-based approach integrating deep reinforcement learning and hybrid genetic algorithm for dynamic scheduling for Industry 3.5 smart production

Dynamic scheduling is crucial for semiconductor manufacturing as product-mix is increasing with shortening product life cycle. However, the present problem is challenging owing to complicated constraints and short time for decision making. Focusing on realistic needs, this research aims to develop a novel agent-based approach that integrates deep reinforcement learning and hybrid genetic algorithm for the unrelated parallel machine scheduling problem with sequence-dependent setup time. In particular, deep Q network (DQN), a combination of deep learning and Q learning, is employed to train a scheduling agent. A trained agent could perform job allocation tasks in short computation time for addressing the dynamic scheduling problem. Furthermore, the proposed hybrid genetic algorithm is employed to enhance searching effectiveness and efficiency during the training process. To estimate the validity, scenarios are designed to compare the developed solution with a number of dispatching rules and other knowledge-based approaches. The experimental results have shown practical viability of the developed solution. Indeed, the developed solution is implemented in a semiconductor manufacturing company.

Factors Influencing Workplace Health Promotion Interventions for Workers in the Semiconductor Industry According to Risk Levels of Chronic Disease

(1) Background: This study aimed to analyze the risk of chronic diseases including hypertension, diabetes, and dyslipidemia in workers of a semiconductor manufacturing company and the factors associated with their participation in workplace health promotion (WHP) programs. (2) Methods: Subjects were workers in a semiconductor and liquid crystal display company in South Korea who had undergone regular health checkups. Data from regular health checkups and WHP interventions were analyzed. Health risk was classified based on the diagnosed disease, in-house classification criteria, and pooled cardiovascular risk score. (3) Results: The baseline characteristics of 39,073 participants included the following: male, 67.8%; between 30 and 40 years of age, 74.1%; <2 h of physical activities, 65.9%. Workers at risk of chronic diseases accounted for 22.2%, and 20.1% were suspicious cases of chronic diseases. Body mass index, and cholesterol level were relatively high in workers with the burden of chronic diseases. The participation rate in WHP programs was 28.8% in a high-risk group among workers at risk of chronic diseases. More participation was shown in male, older age groups, production work type, and single-person household. (4) Conclusions: Because of the low participation rate in WHP activities among workers with the burden of chronic diseases, it is necessary to establish measures to encourage their participation.

A 2.3–5-GHz LC-VCO With Source Damping Resistors to Suppress 1/f Noise Up-Conversion

Two RF CMOS voltage-controlled oscillators (VCOs) with source damping resistors to suppress 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise up-conversion are presented in this letter. Two important parameters: the phase deviation from the first harmonic term of the ideal impulse sensitivity function (ISF), and the initial phase of the first harmonic term of channel current, dominate the 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise up-conversion. Based on the outcome, the effects of the source damping resistors on the two phases are analyzed and two VCO prototypes are designed. Implemented in Taiwan Semiconductor Manufacturing Company 180 nm RF CMOS process, the VCOs achieve 64.7% and 50% frequency tuning range at 2.3–4.5 and 3–5 GHz, respectively, and perform phase noise (PN) of −131.03, −129.28, and −124.98 dBc/Hz at 1 MHz offset from output frequencies of 2.33, 3.057, and 4.57 GHz separately.

An Adaptive STDP Learning Rule for Neuromorphic Systems.

The promise of neuromorphic computing to develop ultra-low-power intelligent devices lies in its ability to localize information processing and memory storage in synaptic circuits much like the synapses in the brain. Spiking neural networks modeled using high-resolution synapses and armed with local unsupervised learning rules like spike time-dependent plasticity (STDP) have shown promising results in tasks such as pattern detection and image classification. However, designing and implementing a conventional, multibit STDP circuit becomes complex both in terms of the circuitry and the required silicon area. In this work, we introduce a modified and hardware-friendly STDP learning (named adaptive STDP) implemented using just 4-bit synapses. We demonstrate the capability of this learning rule in a pattern recognition task, in which a neuron learns to recognize a specific spike pattern embedded within noisy inhomogeneous Poisson spikes. Our results demonstrate that the performance of the proposed learning rule (94% using just 4-bit synapses) is similar to the conventional STDP learning (96% using 64-bit floating-point precision). The models used in this study are ideal ones for a CMOS neuromorphic circuit with analog soma and synapse circuits and mixed-signal learning circuits. The learning circuit stores the synaptic weight in a 4-bit digital memory that is updated asynchronously. In circuit simulation with Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS process design kit (PDK), the static power consumption of a single synapse and the energy per spike (to generate a synaptic current of amplitude 15 pA and time constant 3 ms) are less than 2 pW and 200 fJ, respectively. The static power consumption of the learning circuit is less than 135 pW, and the energy to process a pair of pre- and postsynaptic spikes corresponding to a single learning step is less than 235 pJ. A single 4-bit synapse (capable of being configured as excitatory, inhibitory, or shunting inhibitory) along with its learning circuitry and digital memory occupies around 17,250 μm2 of silicon area.

An Extended-Gate Field-Effect Transistor Applied to Resistive Divider Integrated With the Readout Circuit Using 180nm CMOS Process for Uric Acid Detection

In this work, an extended-gate field-effect transistor (EGFET) applied to resistive divider integrated with the low unity-gain frequency and power consumption instrumentation amplifier (UGFPCIA) was developed successfully in a chip by the Taiwan Semiconductor Manufacturing Company (TSMC) 180nm CMOS process technology. The EGFET was designed based on the uricase/ruthenium dioxide (RuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) sensing film to detect uric acid. The EGFET resistive divider achieved an effective measurement system due to its simplicity, convenience, and low cost. The current properties of EGFET based on the uricase/ RuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> sensing film were also investigated using a semiconductor parameter analyzer. The uric acid concentration which covered the human body (2mg/dL to 7mg/dL) was applied in the measurement. The experimental results indicated that the EGFET resistive divider had a good uric acid sensitivity of 12.69 mV/(mg/dL), high linearity of 0.997, a fast response time of 8 seconds, hysteresis effect of 1.34 mV, LOD of 0.082 mg/dL, and good selectivity to uric acid.

반도체 제조회사의 근골격계 운동치료 프로그램을 통한 체형교정 효과에 관한 연구

Objective: The aim of this study is to evaluate the cases and effects of preventive management program run by a semiconductor manufacturing company for workers suffered from musculoskeletal pain out of the scope of the current risk assessment of musculoskeletal burden works, and to propose the spread of the program to the same industry.<BR>Background: Currently, risk assessment of musculoskeletal burden works will exempt a company from all legal obligations if the company has no legal musculoskeletal burden works. However, there is still a risk of musculoskeletal disorders among workers even if there are no legal musculoskeletal burden works.<BR>Method: This study examined the correction effects of the body type by using a Back Mapper after 80 workers who complained of musculoskeletal symptoms of turtle neck, flat back, bent back, flat waist, lumbar hyperlordosis and scoliosis, from June 2019 to June 2020, received customized individual exercise therapy.<BR>Results: The individual exercise therapy significantly relived the angles of turtle neck, flat back, bent back, flat waist, and lumbar hyperlordosis (p＜0.05) except for scoliosis (p=0.110).<BR>Conclusion: The legal risk assessment of musculoskeletal burden works is limited to protect workers from developing musculoskeletal disorders in advance. Therefore, to prevent the musculoskeletal disorders of workers in the blind spot of the current law, it is necessary to introduce a musculoskeletal exercise therapy program.<BR>Application: The results of this study can be used as a basis for the introduction of an exercise therapy program even at workplaces that are not obligated to investigate legal risk assessment of musculoskeletal burden works.

LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement of 5G NR systems. Although the increase in parallelism can efficiently enhance the throughput, the hardware implementation required to support high parallelism is a significant hardware burden. To efficiently reduce the hardware burden, we used a grouping search rather than a sorter, which was used in the minimum finder with decoding performance loss. Additionally, we proposed a compensation scheme to improve the decoding performance loss by revising the probabilistic second minimum of a grouping search. The post-layout implementation of the proposed dual-mode LDPC decoder is based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) technology, using a compensation scheme of grouping comparison for 5G communication systems with a working frequency of 294.1 MHz. The decoding throughput achieved was at least 10.86 Gb/s without evaluating early termination, and the decoding power consumption was 313.3 mW.