Abstract
This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement of 5G NR systems. Although the increase in parallelism can efficiently enhance the throughput, the hardware implementation required to support high parallelism is a significant hardware burden. To efficiently reduce the hardware burden, we used a grouping search rather than a sorter, which was used in the minimum finder with decoding performance loss. Additionally, we proposed a compensation scheme to improve the decoding performance loss by revising the probabilistic second minimum of a grouping search. The post-layout implementation of the proposed dual-mode LDPC decoder is based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) technology, using a compensation scheme of grouping comparison for 5G communication systems with a working frequency of 294.1 MHz. The decoding throughput achieved was at least 10.86 Gb/s without evaluating early termination, and the decoding power consumption was 313.3 mW.
Highlights
The market for fifth-generation (5G) communication systems is rapidly growing. 5G technology requires low-power and low-cost hardware equipment support because it considers the application requirements of enhanced mobile broadband and massive machine-type communication
The basic idea of the proposed improved normalized probabilistic min-sum algorithm (INPMSA) is that an increase in the error probability of the probabilistic second minimum is due to an increase in the proportion of the first minimum used for improvement
It is worth noting that the studies in [23,24] focused on the low code-rate low-density parity-check (LDPC) decoding and this study focused on the high code-rate LDPC decoding for the 5G NR systems
Summary
The market for fifth-generation (5G) communication systems is rapidly growing. 5G technology requires low-power and low-cost hardware equipment support because it considers the application requirements of enhanced mobile broadband (eMBB) and massive machine-type communication (mMTC). Many approximations exist for the sum-product algorithm originally used in the LDPC, such as simplified versions of the normalized min-sum algorithm (NMSA) [7], the offset min-sum algorithm (OMSA) [8], and the normalized probabilistic min-sum algorithm (NPMSA) [9] These studies simplify the hardware area, reduce the complexity of routing, and speed up the overall operation speed. We propose a flexible compensation scheme based on the NPMSA to achieve hardware simplification and recovery error correction ability. Based on these characteristics, we introduce the proposed compensation scheme to recover the decoding capability and maintain hardware simplification.
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