Development Of Semiconductor Industry Research Articles

Exploration of International Division of Labor Model for Semiconductor Industry Development

Semiconductor design and manufacturing capabilities have become a significant indicator to measure a country's scientific and technological level. Currently, China's semiconductor industry is experiencing accelerated growth, but it still faces challenges such as low localization rates, inadequate long-term industry support and investment, limited independent innovation by enterprises, weak upstream and downstream collaboration, and insufficient talent cultivation and incentive mechanisms. This paper will carefully analyze the developmental traits of the worldwide semiconductor industry as well as its foremost enterprises, investigate the model of global specialization, and propose pertinent developmental suggestions concerning the crucial challenges confronting the domestic semiconductor industry at present.

Financial Policy of Government support for semiconductors Industry Globally and in Russia under sanctions

The relevance of this study is determined by the need to develop the domestic semiconductors industry in Russia, taking into account the negative effects both internal and external.The purpose of this paper is to test the hypothesis of the positive impact of the methods used by the state of financial support of domestic companies to acquire advanced technologies in a specific area in the context of a lack of funding and the significant lag of the national semiconductor industry in the world’s leading countries.The target of this study is the analysis of possible tools of state support, including subsidies and grants, and methods of their application for the creation of competitive industry of domestic semiconductor production.The key methods used in this study include the collection and processing of statistical data, their comparative analysis, as well as the elaboration of the regulatory framework on tax regulation in this sector of the economy.The main methods applied in this study are data collection and processing, comparative analysis, and the development of a regulatory framework for tax regulation in this sector of the economy. The authors analyzed the semiconductors industry in the world, including the production of microprocessors and other semiconductor components. The situation in countries such as China, USA, Japan, Europe, Taiwan, India and Russia is discussed in more detail. The main problems with semiconductor industry development in Russia have been revealed. Additionally, researchers have evaluated and outlined fields of federal budget spendings in the industry in the period of years 2022 and 2025.The scientific novelty of this paper is to identify the relationship between the measures of state tax incentives provided to the radio-electronic industry and macroeconomic indicators. Based on that authors have developed evaluation criteria of the relevance and efficiency of fiscal preferences for the analyzed industry which is considered as the result of research.It concluded that the state’s initiatives to promote the radio-electronics industry might provide Russia a chance to catch up to the world’s leading countries in this industry.

Controlling For X: Export Controls and Emerging Technology Competition

The prevailing view in Washington is that the United States and China are in a fierce competition for control of critical technologies of the future. The Biden Administration’s October 2022 semiconductor export control rules target China’s ability to make or obtain the most advanced semiconductors – the foundational components of advanced technologies. It is best to understand the United States semiconductor export controls as a tool being wielded by the US government in a fight for global technological dominance, particularly in the realm of AI. This strategy represents a substantial assertion of extraterritorial power by the United States, increases the risk of catastrophic conflict between the United States and China, and has the potential to backfire by accelerating China’s domestic semiconductor industry development. The United States should consider easing elements of the semiconductor export controls in exchange for diplomatic concessions, such as greater bilateral military communication, and focus more attention on increasing domestic production of advanced semiconductor technologies by fast tracking expert visas and permitting for new semiconductor fabrication facilities.

Epitaxial growth of atomically thin Ga2Se2 films on c-plane sapphire substrates

Broadening the variety of two-dimensional (2D) materials and improving the synthesis of ultrathin films are crucial to the development of semiconductor industry. As a state-of-the-art 2D material, Ga2Se2 has attractive optoelectronic properties when it reaches the atomically thin regime. However, its van der Waals epitaxial growth, especially for atomically thin films, has seldom been studied. In this paper, we used molecular beam epitaxy to synthesize Ga2Se2 single-crystal films with a surface roughness down to 1.82 nm on c-plane sapphire substrates by optimizing the substrate temperature, Se:Ga flux ratio, and growth rate. Then, we used a three-step mode to grow Ga2Se2 films with a thickness as low as three tetralayers and a surface roughness as low as 0.61 nm, far exceeding the performance of direct growth. Finally, we found that surface morphology strongly depends on the Se:Ga flux ratio, and higher growth rates widened the suitable flux ratio window for growing Ga2Se2. Overall, this work advances the understanding of the vdW epitaxy growth mechanism for post-transition metal monochalcogenides on sapphire substrates.

Optically and Electrically Controllable Light-Emitting Nonvolatile Resistive Switching Memory

Resistive switching memory (RSM) emerges as a decisive player for the future development of semiconductor industry due to its many advantages, such as high speed, cost effectiveness, excellent scalability, and compatibility with current technology. However, the electrical reading of the RSM array is usually in series sequence, which limits its maximum data storage density and processing speed. This drawback can be overcome by optically readable memory devices. Herein, we demonstrate an unprecedented optically and electrically controllable light-emitting RSM. This device uses a tandem structure which is composed of a light-emitting RSM and a perovskite solar cell. The state of the device can be encoded both electrically and optically, with high-resistive state and low-resistive state. Interestingly, the device exhibits electroluminescence in the low-resistive state, which provides the capability for reading the encoded signal optically. By integrating with a solar cell, the whole device enables to assist on the light-emitting RSM to achieve the unique feature of optical writing. Compared with conventional memory, our designed device with multiple functionalities of optical/electrical encoding and electrical/optical reading should be very useful and timely for the development of next-generation information technology.

Synthesis of Silicon Nitride Nanoparticles by Upcycling Silicon Wafer Waste Using Thermal Plasma Jets.

Silicon (Si) waste generation is a critical issue in the development of semiconductor industries, and significant amounts of Si waste are disposed via landfilling. Herein, we propose an effective and high value-added recycling method for generating nitride nanoparticles from Si waste, such as poor-grade Si wafers, broken wafers, and Si scrap with impurities. Si waste was crushed and used as precursors, and an Ar-N2 thermal plasma jet was applied at 13 kW (300 A) under atmospheric pressure conditions. A cone-type reactor was employed to optimize heat transfer, and Si waste was injected into the high-temperature region between the cathode and anode to react with free/split nitrogen species. Spherical Si3N4 nanoparticles were successfully synthesized using isolated nitrogen plasma in the absence of ammonia gas. The crystalline structure comprised mixed α- and β-Si3N4 phases with the particle size <30 nm. Furthermore, the influence of ammonia gas on nitridation was investigated. Our findings indicated that Si3N4 nanoparticles were successfully synthesized in the absence of ammonia gas, and their crystallinity could be altered based on the reactor geometry. Therefore, the as-proposed thermal plasma technique can be used to successfully synthesize high value-added nanopowder from industrial waste.

Analysis on Current Situation and Countermeasures of Semiconductor Industry Development

As a cutting-edge technology and high value-added industry, semiconductor has gradually developed into a pillar industry of global economic growth. After several years of technology accumulation and achievement stack, Hefei semiconductor industry has formed a large-scale, systematic and diversified industrial layout, but the "bottleneck" and challenges can not be ignored. Based on the current situation and existing problems of Hefei semiconductor industry development, this paper puts forward relevant countermeasures and suggestions to break through the bottleneck and help the industry boosting, in order to give suggestions for the iterative upgrading of Hefei semiconductor industry.

Study on Teaching System of Semiconductor Device Physics under Information Background

At present, semiconductor is a relatively weak industry in our country. It’s ustainable and healthy development is related to our county’s scientific and technological innovation, economic prosperity as well as national security. Semiconductor device physics, as a very important required course for semiconductor major, has far-reaching influence on the development of semiconductor industry. However, it is dull and difficult to understand especially for the traditional teaching method. Here, some reformation of the teaching methods of semiconductor device physics under information background are put forward. These methods can attract students to participate in class and become masters of learning to some extent.

(Invited) Advanced ALD Applications

CMOS device feature size down-scaling is still continuous. Nowadays it reaches 5nm and beyond. The technology development in semiconductor industry encounters many new challenges. As consequences, new materials and new techniques are required to meet the challenges.At 45nm technology node, Atomic Layer Deposition (ALD) is introduced for gate stack process. Since then ALD is being used more and more in advanced technology nodes because of its intrinsic process features, e.g. accurate thickness control and excellent step coverage etc. Especially for the reduced feature sizes, ALD exhibits as a powerful technique, not only in gate stack, but also in advanced patterning process (SADP and SAQP) and advanced metallization barrier materials etc.Hf-based hik material deposited by ALD is widely used in logic gate stack and memory capacitor. Recently Hf-based materials are continuously getting more attentions due to its intrinsic features. It is reported that Hf-based materials can exhibit different resistor stage. Therefore it can be used as memristor in ReRAM. People also report Hf-based materials can be crystalized into orthorhombic phase and thus exhibit ferroelectric characteristics[1,3]. Based on this feature, it can be used in NCFET and FeRAM. In this paper, we can going to review the applications of Hf-based materials deposited by ALD in new memory fields.Although device down-scaling is still going on, the challenges are tremendous. As an alternative, 3D-IC packaging, stacks different chip together and increases the packaging density and chip performance. Therefore, recently 3D-IC packaging is getting more and more attractive. However, there are many constrains in 3D-IC packaging, e.g. low thermal budget, high aspect ratio structure, excellent film quality etc.. ALD is gradually accepted in 3D-IC packaging due to its intrinsic features. In this paper, we are going to discuss some ALD applications in advanced 3D-IC packaging.REFERENCES[1] J. Müller et al, NanoLetters, vol. 12, no. 8, pp. 4318-4323, 2012.[2] M. H. Lee et al, IEEE J. of the Electron Device Society, vol. 3, no. 4, pp. 377-381, 2015.[3] M. H. Lee et al, IEEE Electron Device Letter, vol. 36, no. 4, pp. 294-296, 2015.

A Boosting Regression-Based Method to Evaluate the Vital Essence in Semiconductor Industry Performance

In accordance with the statistical analysis, the industrial performance is usually related to research and development (R&D) intensity, and this factor indeed plausibly brings the biggest profit with patents and supporting products to the development of semiconductor industry. How to evaluate the completive performance of modern industries is an increasing issue, especially for the semiconductor industries in these decades. However, almost every traditional statistical model is deterred by the hypothesis of population and independent correlation among each feature, and this makes the result of typical regression model potentially lose reliability. To avoid this weakness, this article therefore applies a gradient boosting based method - XGBoost to evaluate the feature importance of semiconductor industries. In the simulation experiments, different findings revel certain information, apart from R&D intensity, actually sway the gross net value in the annual financial announcement of semiconductor industries. Moreover, this article proposes another concept to evaluate the essential factor contributing the development of semiconductor industries. Instead of only focusing on the effect of R&D intensity, this article also predicts the future growth rate (GR) of net value by applying the greedy search of XGBoost Regression.

A efficacy of different buffer size on latency of network on chip (NoC)

Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.

Rationale of the need to the development of semiconductor industry in Russia with the 28 nanometer semiconductor device fabrication node and below

This article describes the systemic problem of the development of the Russian semiconductor industry due to the lack of national production of integrated microcircuits with topological standards below 65 nm. Here are the results of the analysis of the feasibility of production lines of integrated circuits developing, depending on the forecasted volume of demand for various categories of semiconductor products, the technological backlog of Russian organizations and the estimated cost of the project. In this article, there are suggestions on possible sources of project financing and measures of non-financial support. Also, it describes the general technological parameters of the created production. It contains an assessment of key performance indicators of the project and the impact of its implementation on related technological areas.

Stable Li Ion Batteries Anode By Inducing the Covalent Bond between Active Material and Binder By Esterification Reaction

Lithium ion batteries (LIBs) has been the main energy storage medium for portable electronics since the commercialization by Sony Corporation since 1991. Ever growing demand for large-scale energy storage devices such as electrical vehicles requires the high energy density and long cycle life LIBs that could not be attained by the currently used battery. Graphite is the most common anode material in commercial LIBs, but its specific capacity is relatively low (372 mAh g-1) with a poor rate capability, which does not meet the high demand for large-scale applications. Silicon (Si) is one of the most promising anode candidates due to its high theoretical specific capacity (3579 mAh g-1 for Li15Si4), relatively low discharge potential (~0.4V vs Li+/Li), and abundance in nature. However, Si goes through a dramatic volume change during cycling and thus undergoes a drastic structural deformation, which induces loss of electrical contact between Si and current collector, breakdown of solid electrolyte interphase (SEI) layer, and Si aggregation during cycling, eventually resulting in failure of cyclic performance. Although design a various nanostructure forms or introduction of secondary phase layers has been realized as a method to achieve high-performance Si anode, these methods require complex reactions such as hydrothermal or template-assisted synthesis and usually involve hazardous reagents like SiH4 or HF, which eventually result in cost and barrier to scale up. From the practical view, use of commercial Si is the most promising, where the commercial production of Si has been benefitted from the development in semi-conductor industry. Conventionally, battery is prepared by mixing active materials and binder with conducting agent in organic solvent to produce viscous slurry and blading onto copper current collector. Recently, the selection of binder has turned out to play critical role in the battery performance as maintaining the structural integrity of electrode film. It has been revealed that carboxylic acid or hydroxyl functional groups terminated binders which is commercially available, such as polyacrylic acid (PAA), carboxymethyl cellulose (CMC or Na-CMC) or alginate (Alg or Na-Alg) binder, can result in enhanced cycling performance utilizing the hydrogen bonding interactions with the native oxide on Si, compared to that of conventional PVDF binder which has no functional group and bonds weekly with Si through a week Van der Waals interaction. Nonetheless, due to the linear chain characteristic of these binders, susceptible sliding upon the continual volume change of Si results in the contact loss between binder and Si, which eventually results in the irreversible capacity failure. Herein, we propose a novel concept that can achieve stable Si anode by transitioning the bonding nature between binder and Si from hydrogen bond to mechanically robust covalent bond, which can effectively restrain any large movement of Si, and eventually prevent the destruction of the electrical network during cycling. Inducing the esterification reaction between binder and Si can be an efficient method to form a covalent bond between those two materials. (eq. (1)) R-COOH+HO-R’ -> R-COO-R’+ H2O -------- (1) To induce an esterification reaction between binder and Si, three crucial points have to be addressed. First, as carboxylate (–COO-) functional group terminated binder such as Na-CMC can hardly react with the hydroxyl functional group (-OH), PAA binder which is terminated with the carboxylic acid functional group (-COOH) has been selected in our system. Second, while commercially purchased Si has a –OH functional group by a partially hydrolyzed SiO2 layer covering the Si particles, its functional group density is insufficient for an esterification reaction to take place. Therefore, terminating –OH functional group at the surface of Si is crucial factor to increase the site to react with PAA binder. Third, due to kinetically sluggish characteristic of esterification reaction, proper usage of esterification catalyst is required. Experimental procedure is as follows; firstly, as-received Si was pretreated in piranha solution to terminate –OH. Then, –OH terminated Si was prepared into slurry by mixing with Super-P and PAA binder, casted onto copper foil, dried overnight and punched for a coin-type cell. To induce the esterification reaction, punched cell was dipped into sodium hypophosphite catalyst solution and then annealed in 180 °C for 1 h. Three counter groups are denoted as HB-Cell (punched cell with no annealing process), PE-Cell (annealed cell without usage of sodium hypophosphite), and FE-Cell (annealed cell with addition of sodium hypophosphite.) The fabricated FE-Cell exhibits superior cycle stability (2200 mAh g-1 at 100 cycles) compare to HB-Cell or PE-Cell, demonstrating the effect of covalent bond on obtaining the high-performance Si anode. Figure 1

The tensile effect on crack formation in single crystal silicon irradiated by intense pulsed ion beam

Improving antifatigue performance of silicon substrate is very important for the development of semiconductor industry. The cracking behavior of silicon under intense pulsed ion beam irradiation was studied by numerical simulation in order to understand the mechanism of induced surface peeling observed by experimental means. Using molecular dynamics simulation based on Stillinger Weber potential, tensile effect on crack growth and propagation in single crystal silicon was investigated. Simulation results reveal that stress-strain curves of single crystal silicon at a constant strain rate can be divided into three stages, which are not similar to metal stress-strain curves; different tensile load velocities induce difference of single silicon crack formation speed; the layered stress results in crack formation in single crystal silicon. It is concluded that the crack growth and propagation is more sensitive to strain rate, tensile load velocity, stress distribution in single crystal silicon.

Sustainable Energy Source for Wearable Electronics Based on Multilayer Elastomeric Triboelectric Nanogenerators

Wearable electronics have attracted a wide range of attention with various functions due to the development of semiconductor industry and information technology. This work focuses on a triboelectric nanogenerator‐based self‐charging power system as a continuous energy source for wearable electronics. The triboelectric nanogenerator has a multilayer elastomeric structure with closely stacked arches as basic functional units. Owing to material and structural innovations, this triboelectric nanogenerator performs outstanding electric output with the maximum volume charge density ≈0.055 C m−3 and practical properties for energy harvesting from body motions. Utilizing the triboelectric nanogenerator as outsole to harvest energy from walking or jogging, a pair of shoes is fabricated with the maximum equivalent charge current of each shoe being around 16.2 µA and specific fitness functions realized on each shoe separately without complex connections.

China's Bold Strategy for Semiconductors Zero-Sum Game or Catalyst for Cooperation?

This paper explores whether China's bold strategy for semiconductors will give rise to a zero-sum game or whether it will enhance cooperation that will benefit from increased innovation in China.As the world's largest producer and exporter of electronic products, China is by far the top market for integrated circuits (ICs), accounting for nearly a third of global demand. Yet its ability to design and produce this critical input remains seriously constrained. Despite decades and many billions of dollars of state-led investment, China's domestic production of semiconductors covers less than 13% of the country's demand. As a result, China's IC trade deficit has more than doubled since 2005, and now has surpassed crude oil to become China's biggest import item. To correct this unsustainable imbalance, China seeks to move from catching up to forging ahead in semiconductors through progressive import substitution. The National Semiconductor Industry Development Guidelines (Guidelines) and the Made in China 2025 (MIC 2025) plan were published by China's State Council in June 2014 and May 2015, respectively. Both plans are backed by huge investments and a range of support policies covering intellectual property, cybersecurity, procurement, standards, rules of competition (through the Anti-Monopoly Law), and the negotiation of trade agreements, like the Information Technology Agreement. The objective is to strengthen simultaneously advanced manufacturing, product development and innovation capabilities in China's semiconductor industry as well as in strategic industries that are heavy consumers of semiconductors. Until recently, China has focused primarily on logic semiconductors and mixed-signal integrated circuits for mobile communication equipment (including smart phones), and on the assembly, testing and packaging of chips. Since the start of the 13th FYP, China's semiconductor industry strategy now covers a much broader range of products and value chain stages, while at the same time increasing the depth and sophistication of its industrial upgrading efforts. This important new development is at the center of this paper. Based on a review of policy documents and interviews with China-based industry experts, I will describe key policy initiatives and stakeholders involved in the current strategy; highlight important recent adjustments in the strategy to broaden China's semiconductor product mix; and assess the potential for success of China's ambitious efforts to diversify into memory semiconductors, analog semiconductors, and new semiconductor materials (compound semiconductors). The chances for success are real, giving rise to widespread worries in the US and across Asia that China's bold strategy for semiconductors may result in a zero-sum game with disruptive effects on markets and value chains. However, Chinese semiconductor firms still have a long way to go to catch up with global industry leaders. Hence, global cooperation to integrate China into the semiconductor value chain makes more sense than ever, both for the incumbents and for China.

Advanced Wet Clean Technology at Lightly Doped Drain Layers in FinFET

Along with fast-paced development of semiconductor industry, circuit patterns become much smaller and finer. Currently the pattern design migrates from traditional planar structure to three-dimensional FinFET. Therefore how to remove surface particles in various sizes effectively without damaging the pattern structures in the higher aspect ratio is more and more essential to achieving critical rapid yield ramps in the advanced technology node. In the FinFET process scheme, after formation of poly gate, Lightly Doped Drain (LDD) implants are invented to alleviate the short channel effect between Source and Drain Junction. In LDD layers, low density impurity of B+ and As+are implanted into PFET and NFET, respectively. The repeated implant steps will inevitably bring certain amount of surface particles, which are defined in higher killer ratio, since they can be embedded defect after few nitride spacer layers are deposited, causing the poor device performance and low product yield. Figure 1 shows the typical SEM images of various surface particles generated during repeated LDD implant steps. Standard RCA Clean 1 (SC1) with the mixture of hydrogen peroxide, ammonium hydroxide and deionized water usually would be applied to reduce organic and surface particle. But particles removal efficiency (PRE) is not satisfied for advanced FinFET manufacturing. Aerosol or nanospray to dispense chemical solution with the mixture of nitrogen gas in high pressure is another candidate to possess higher PRE, however, the traditional aerosol technique would create liquid droplets in a large range of size, so the non-uniformed momentum of liquid droplet can result in severe pattern damage on poly gate at LDD layers. In this paper, we report an advanced wet clean method based a single wafer clean toolset. By using this state-of-the-art wet clean technology, we can control the size and velocity of liquid droplets accurately during the clean chemical dispense. In this sense, with high PRE for surface particles, in the meantime, there is no sacrifice of gate pattern damage in LDD layers. It was demonstrated on FinFET production wafers that surface particles were reduced by as much as 30% with the new clean technology implementation. Also, about 5% yield improvement was observed for the new clean process. Figure 1: Typical SEM images of surface particle defect in LDD layers Figure 1

A survey of routing algorithm for mesh Network-on-Chip

With the rapid development of semiconductor industry, the number of cores integrated on chip increases quickly, which brings tough challenges such as bandwidth, scalability and power into on-chip interconnection. Under such background, Network-on-Chip (NoC) is proposed and gradually replacing the traditional on-chip interconnections such as sharing bus and crossbar. For the convenience of physical layout, mesh is the most used topology in NoC design. Routing algorithm, which decides the paths of packets, has significant impact on the latency and throughput of network. Thus routing algorithm plays a vital role in a wellperformed network. This study mainly focuses on the routing algorithms of mesh NoC. By whether taking network information into consideration in routing decision, routing algorithms of NoC can be roughly classified into oblivious routing and adaptive routing. Oblivious routing costs less without adaptiveness while adaptive routing is on the contrary. To combine the advantages of oblivious and adaptive routing algorithm, half-adaptive algorithms were proposed. In this paper, the concepts, taxonomy and features of routing algorithms of NoC are introduced. Then the importance of routing algorithms in mesh NoC is highlighted, and representative routing algorithms with respective features are reviewed and summarized. Finally, we try to shed light upon the future work of NoC routing algorithms.

Ni-Pd 합금 전해도금의 특성에 관한 연구

The test equipment becomes more important with the development of semiconductor industry. MEMS probe is an important testing component to detect the defects from the generated electric signal when it contacts the metal pad of semiconductor devices. Ni-Pd alloy has been paid attention to as a candidate of MEMS probe material because of its high surface hardness and relatively low resistivity. In this study, electroplated Ni-Pd alloy has been prepared by using ethylene diamine as a complexing agent. Solid solution alloy coating could be formed when concentration of palladium chloride and current density were in the ranges of 1~5 mM and <TEX>$0.2{\sim}1.5A/dm^2$</TEX>, respectively. The increase of current density brought about an decrease in palladium content, which made both of lattice parameter and grain size smaller. As a result of grain refinement, high hardness could be obtained. However, surface cracking was observed due to residual stress when the current density was above <TEX>$1.3A/dm^2$</TEX>. When effects of heat treatment temperature on hardness and sheet resistance were investigated, the accompanied grain growth decreased both of them. The decrease of hardness remained stable at a temperature of <TEX>$200^{\circ}C$</TEX>. The sheet resistance was drastically reduced at <TEX>$100^{\circ}C$</TEX>. After that, it was found to become constant.

Session-based security enhancement of RFID systems for emerging open-loop applications

Radio frequency identification (RFID) is an important technique used for automatic identification and data capture. In recent years, low-cost RFID tags have been used in many open-loop applications beyond supply chain management, such as the tagging of the medicine, clothes, and belongings after the point of sales. At the same time, with the development of semiconductor industry, handheld terminals and mobile phones are becoming RFID-enabled. Unauthorized mobile RFID readers could be abused by the malicious hackers or curious common people. Even for authorized RFID readers, the ownership of the reader can be transferred and the owners of the authorized mobile reader may not be always reliable. The authorization and authentication of the mobile RFID readers need to take stronger security measures to address the privacy or security issues that may arise in the emerging open-loop applications. In this paper, the security demands of RFID tags in emerging open-loop applications are summarized, and two example protocols for authorization, authentication and key establishment based on symmetric cryptography are presented. The proposed protocols adopt a timed-session-based authorization scheme, and all reader-to-tag operations are authorized by a trusted third party using a newly defined class of timed sessions. The output of the tags is randomized to prevent unauthorized tracking of the RFID tags. An instance of the protocol A is implemented in 0.13-μm CMOS technology, and the functions are verified by field programmable gate array. The baseband consumes 44.0 μW under 1.08 V voltage and 1.92 MHz frequency, and it has 25,067 gate equivalents. The proposed protocols can successfully resist most security threats toward open-loop RFID systems except physical attacks. The timing and scalability of the two protocols are discussed in detail.