Semiconductor Field-effect Transistor Structure Research Articles

The effect of water related traps on the reliability of organic based transistors

The electrical stability of metal–insulator–semiconductor (MIS) capacitors and field-effect transistor structures based in organic semiconductors were investigated. The device characteristics were studied using steady state measurements AC admittance measurements as well as techniques for addressing trap states. Temperature-dependent measurements show clear evidence that an electrical instability occurs above 200K and is caused by an electronic trapping process. Experimental results show that water is responsible for the trapping mechanism.

Comparison of ZnO metal–oxide–semiconductor field effect transistor and metal–semiconductor field effect transistor structures grown on sapphire by pulsed laser deposition

ZnO thin film field effect transistors with 1.5–20μm gate width were fabricated using either a metal gate [metal–semiconductor field effect transistor (MESFET)] or a metal–oxide–semiconductor (MOS) gate. In both cases we found that use of a thick (∼0.8–0.9μm) ZnO buffer was necessary on the sapphire or glass substrate prior to growing the active layers in order to reduce gate leakage current. Source/drain contacts of e-beam deposited Ti∕Al∕Pt∕Au showed specific contact resistances of 2.18×10−6Ωcm2 without annealing and the interdevice isolation currents were ∼10μA at 40V bias. The MOS structure with 50nm (Ce,Tb)MgAl11O19 gate dielectric showed a 1 order of magnitude lower gate leakage current than the MESFET, due to the relatively low barrier height of metals on n-type ZnO (0.6–0.8eV). Good drain–source current characteristics were obtained from MOS gate structures using P-doped ZnO channels, whereas the metal structures showed very poor modulation.

Improvement in epitaxial quality of selectively grown Si 1−xGe x layers with low pattern sensitivity for CMOS applications

The selective growth of Si 1− x Ge x structures ( 0.09 < x < 0.29 ) on patterned substrates aimed for channel layer application in metal oxide semiconductor field effect transistor (MOSFET) structures by using chemical vapor deposition (CVD) has been investigated. By optimizing the growth parameters, the surface roughness of these structures was improved and layers with better epitaxial quality was obtained. Furthermore, two methods are proposed to decrease the pattern-dependency of the epitaxy process. The key point in these methods is based on the reduction of surface diffusion of the adsorbed species on the oxide. This can be obtained by introducing square polycrystalline Si stripes around the oxide openings acting as diffusion barriers. Subsequently, chemical mechanical polishing was performed to remove the polycrystalline stripe on the oxide. Evaluation of the proposed solutions for issues such as defect generation and the possibility for integration in device structures have also been performed.

AlGaN/GaN polarization-doped field-effect transistor for microwave power applications

We discuss an AlGaN/GaN metal–semiconductor field-effect transistor (MESFET) structure grown without any impurity doping in the channel. A high-mobility polarization-induced bulk channel charge was created by grading the channel region linearly from GaN to Al0.3Ga0.7N over 1000 Å. This polarization-doped FET (PolFET) was fabricated and tested under dc and rf conditions. Current density of 850 mA/mm and transconductance of 93 mS/mm was observed under dc conditions. The 0.7 μm gate length devices had a cutoff frequency, fτ=19 GHz, and maximum oscillation frequency, fmax=46 GHz. We demonstrate that the PolFETs perform better than comparable MESFETs with impurity-doped channels, and are suitable for high power microwave applications. An important advantage of these devices over AlGaN/GaN high electron mobility transistors is that the transconductance versus gate voltage profile can be tailored by compositional grading for better large-signal linearity.

Multiple Bit Operation of MFISFET With Pt/SrBi2Ta2O9/Y2O3/Si Gate Structure

A single transistor type ferroelectric memory with multiple bit operation was presented. This cell has a metal ferroelectric insulator semiconductor field effect transistor structure. Y2O3 thin film was used as a buffer insulating layer to improve the memory characteristics and SrBi2Ta2O9 was used as a ferroelectric gate material. The multi-level characteristics of four levels with one order of drain current difference were measured according to the writing voltage step of two volt. This multi-level memory cell enables to increase the density of memory in the same space and lower the cost.

Micro-Raman investigations of the degree of relaxation in thin SiGe buffer layers with high Ge content

Virtual substrates with high Ge content x of 0.25<x<0.5 for metal oxide semiconductor field effect transistor (nMOSFET) structures are grown by molecular beam epitaxy (MBE). Thin strain-relaxed SiGe buffers are of special importance for this application, therefore, sub-100 nm layer growth procedures have been developed. Micro-Raman spectroscopy has been extensively employed for measurements of Ge content and the degree of relaxation (r) in our virtual substrates. Two growth stages – a very low temperature (VLT) stage and overgrowth at 550 °C (OT stage) were used to provide the high relaxation in thin SiGe layers. Implementation of this process under careful temperature control within 50 °C during the VLT growth stage allows us to regulate precisely the degree of relaxation. The role of low temperatures and of Sb surfactants during the VLT growth stage for process-window widening is studied. The Sb pre-buildup is found to increase the degree of relaxation in a higher temperature range during the VLT stage. Optimum processing conditions are determined and high uniformity of composition and residual-strain distribution on virtual substrate wafers are demonstrated.

Fabrication and electrical characterization of top gate single-wall carbon nanotube field-effect transistors

We describe the fabrication of single-wall carbon nanotube field-effect transistors in a conventional metal–oxide–semiconductor field-effect transistor structure, with gate electrodes above the conduction channel separated from the channel by a thin dielectric. We use these devices to study the performance improvements achieved by reducing the gate-to-channel separation. The top gate structure offers certain structural advantages over earlier, back gated carbon nanotube devices. In addition, these devices exhibit excellent electrical characteristics, including steep subthreshold slope and high transconductance, at gate voltages close to 1 V. The measured device characteristics are significantly better than previously reported carbon nanotube devices, providing further motivation to explore the use of carbon nanotubes for future nanoelectronic applications.

A novel dissolved oxygen sensor based on MISFET structure with Pt–LaF 3 mixture film

Using carbon paste film forming method, a novel all-solid dissolved oxygen (DO) sensor based on metal insulator semiconductor field effect transistor (MISFET) structure with Pt–LaF 3 mixture film has been developed. In this paper, we have described the device structure. And we have measured the device characteristics, given the response curves of the output voltage (Δ V rs: the reference voltage shift) versus the DO concentration ([O 2]) which were bound at different biases and different temperatures. According to our experimental results, we can come to the conclusion that the device we have proposed is feasible to determine the content of DO.

Controlling the threshold voltage of a metal–oxide–semiconductor field effect transistor by molecular protonation of the Si:SiO2 interface

We present results from a hybrid molecular/metal–oxide–semiconductor field effect transistor (MOSFET) structure that is sensitive to the presence of a molecular monolayer on its surface. The device is fabricated from a silicon-on-insulator substrate, and unlike a conventional MOSFET a substrate voltage is used to invert the buried Si:SiO2 interface. This allows the top surface of the silicon to be free of any insulating layers, apart from a thin native oxide that forms on exposure to air. The buried inversion layer is less than 40 nm away from the exposed surface, and the threshold voltage of the device is strongly influenced by the surface potential. Measurements of the drain current as a function of substrate voltage can be accurately reproduced from numerical simulation by treating the charge at the native oxide interface as a fitting parameter. The shift in threshold voltage after molecular attachment can be accounted for by a simple increase in the (positive) fixed oxide charge density, all of the other parameters being kept constant. This suggests that the shift in threshold voltage occurring after attachment of the molecular monolayer results from protonation of the native oxide. We explain this result in terms of the higher acidity of the molecular group compared to that of the native oxide.

Effects of surface states on control characteristics of nano-meter scale Schottky gates formed on GaAs

Effects of surface states on gate control characteristics of nano-meter scale Schottky gates formed on GaAs are investigated both theoretically and experimentally. Special sample structures are used. They are metal–insulator–semi-conductor structures having nano-meter scale Schottky dot arrays for capacitance–voltage ( C–V) measurements and metal–semi-conductor field effect transistor structures having nano-meter scale grating Schottky gates for current–voltage ( I–V) measurements. Measured C–V and I–V results are compared with results of theoretical calculation on a computer. The effects of surface states are found to be two-fold. Namely, it is shown that control characteristics of nano-meter scale Schottky gates are strongly degraded by the presence of Fermi level pinning caused by surface states on the free surface surrounding the gate. It is also shown that a significant amount of gate-induced lateral charging of surface states takes place around the gate periphery, effectively increasing the gate dimension. These results indicate the critical importance of control of surface states in nano-devices using nano-meter scale Schottky gates.

Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes

We have fabricated single-wall carbon nanotube field-effect transistors (CNFETs) in a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) structure, with gate electrodes above the conduction channel separated from the channel by a thin dielectric. These top gate devices exhibit excellent electrical characteristics, including steep subthreshold slope and high transconductance, at gate voltages close to 1 V—a significant improvement relative to previously reported CNFETs which used the substrate as a gate and a thicker gate dielectric. Our measured device performance also compares very well to state-of-the-art silicon devices. These results are observed for both p- and n-type devices, and they suggest that CNFETs may be competitive with Si MOSFETs for future nanoelectronic applications.

Hydrogen-assisted pulsed-laser deposition of epitaxial CeO2 films on (001)InP

We report on the growth of epitaxial CeO2 on (001) InP using hydrogen-assisted pulsed-laser deposition. Epitaxy is achieved via laser ablation of a CeO2 target in the presence of molecular hydrogen that is introduced during nucleation to reduce native In2O3 from the InP surface. X-ray diffraction scans confirm a cube-on-cube epitaxial relationship between the oxide film and the InP substrate. Rapid heating to the deposition temperature proved important in avoiding significant decomposition of the InP surface prior to film growth. This result should enable the integration of electronic oxide functionality with InP-based semiconductor technologies, and provide a means to explore InP metal–oxide–semiconductor field-effect transistor structures.

A novel high performance stacked LDD RF LDMOSFET

A novel silicon RF lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) structure, using a simple yet effective concept of stacked lightly doped drain (LDD), is proposed. The stacked layers of LDD minimizes the on-state resistance of the transistor due to the n+ doping used in the top LDD layer, and also raises the device breakdown voltage due to the charge compensation in the composite LDD region. Therefore, for the same blocking voltage rating, the stacked LDD structure allows the LDMOSFET to have a higher current handling capability. This in turn causes the transconductance Gm to be higher, leading to higher RF performance for the power device. Measured results show that a 67% improvement in I/sub dsat/ and a 16% improvement in forward blocking voltage are obtained. Furthermore, the new device achieves an increase in transconductance of 145% and improves cut-off frequency by 108% at a gate voltage of 10 V.

Strained Si1−xGex graded channel PMOSFET grown by UHVCVD

The experimental realization of a p-type Si/SiGe heterostructure metal oxide semiconductor field-effect transistor (HMOSFET) structure with a strained Si1−xGex graded well as the conducting channel is reported utilizing ultra-high-vacuum chemical vapor deposition (UHVCVD). The graded variation of the Ge fraction in channel can reduce the relaxation of strained SiGe epilayer. Simultaneously, rapid thermal oxidation (RTO) was used to obtain a high-quality thin-gate oxide films avoiding high thermal budgets which will cause the strain relaxation of graded Si1−xGex layer. The proposed device with a 0.5×100 μm2 gate exhibits a well-done transistor behavior. An extrinsic transconductance of 130 mS/mm at room temperature has been obtained.

Comparison of two-dimensional carrier profiles in metal–oxide– semiconductor field-effect transistor structures obtained with scanning spreading resistance microscopy and inverse modeling

Scanning spreading resistance microscopy (SSRM) is used to determine the complete two-dimensional carrier profile of fully processed 0.29 μm p- and n-type metal–oxide–semiconductor field-effect transistors with various source/drain implants. A comparison is made between the quantified profiles determined using SSRM and the profiles extracted from the electrical device characteristics using an inverse modeling technique. This comparison includes source/drain and well implants, epilayers, and field implants. The data are compared in terms of depth precision and carrier-concentration accuracy and show a good agreement. This article also addresses the limitations and possible artifacts of both methods.

Crystallographic Structures and Parasitic Resistances of Self-Aligned Silicide TiSi2/Self-Aligned Nitrided Barrier Layer/Selective Chemical Vapor Deposited Aluminum in Fully Self-Aligned Metallization Metal Oxide Semiconductor Field-Effect Transistor

In deep submicron metal oxide semiconductor field-effect transistor (MOSFET) structures, parasitic resistances of source/drain and gate (S/D&G) regions limit device performance. For the reduction of parasitic resistances, we have previously proposed a fully self-aligned metallization (FSAM) MOSFET using selective aluminum chemical vapor deposition (Al CVD) technology. The features of FSAM-MOSFET are (1) self-aligned silicide (SALICIDE) for low TiSi2/n+-Si contact resistances in S/D regions, (2) self-aligned barrier layer on TiSi2 surface, and (3) selective Al deposition on S/D&G regions for low sheet resistances. In this study, crystallographic structures and parasitic resistances of SALICIDE TiSi2/self-aligned nitrided barrier layer/selective CVD Al structures have been investigated. It has been experimentally confirmed that (1) C49-TiSi2/n+-Si has lower contact resistance than C54-TiSi2/n+-Si, (2) the 10 nm amorphous Ti–Si–N barrier layer has stable thermal endurance and does not increase the contact resistances, and (3) the selective CVD Al layer reduces the sheet resistances of the S/D. Therefore, the combination of SALICIDE TiSi2, self-aligned barrier layer and selective CVD Al is promising for the low-temperature FSAM-MOSFET process.

Spectroscopy of a silicon quantum dot

We have fabricated a silicon quantum dot embedded in a metal–oxide–semiconductor field-effect transistor structure. Two side gates deplete the quasi-two-dimensional electron gas created by a top inversion gate. We have tested devices ranging in size from 40 to 200 nm. By varying the density with the top gate, the conductance peaks reveal the details of the energy-level structure within the dot and their interactions with one another.

Multiwafer gas source molecular beam epitaxial system for production technology

High throughput epitaxial wafer production is demonstrated by using a newly designed multiwafer gas source molecular beam epitaxy apparatus. The actual application data show excellent results of uniformity, cost performance, and material performance through practical mass production operation. Electron mobility as high as 124 000 cm2/V s is obtained at 77 K for a 7-μm-thick GaAs layer with a carrier concentration of 7.7×1013 cm−3. A typical surface defect density of 25 cm−2 is achieved for continuously grown 1.7-μm-thick metal–semiconductor field effect transistor (MESFET) structures. The uniformity of sheet resistance in n-GaAs and AlAs mole fractions in AlGaAs is less than 2.0% (1.5% and 0.27%, respectively) over a 27 cm diameter area. A quantitative throughput number for a typical growth of a MESFET structure is four 4 in. or seven 3 in. diameter wafers per 2.5 h in a continuous process flow.

Diode Physical Parameters for HEXFETs Characterization of Dose Effect

Modeling techniques of P-N junctions have been applied for studying the physical parameters in metal-oxide semiconductor field-effect transistor structures. A parameter extraction method provides a precise description of the changes in conduction processes due to radiation damages in the integral body-drain junction. A large increase of the ideality factor and series resistance is related to radiation-induced defects.

Pulse-doped diamond p-channel metal semiconductor field-effect transistor

A p-type diamond metal semiconductor field-effect transistor (MESFET) structure, utilizing a boron pulse-doped layer as the conducting channel, has been successfully fabricated. The pulse-doped structure consists of an undoped diamond buffer layer, a highly doped thin diamond active layer, and an undoped diamond cap layer grown by the microwave plasma assisted chemical vapor deposition method. It is shown that this field-effect transistor with a gate length of 4 μm and the gate width of 39 μm exhibits an extrinsic transconductance of 116 μS/mm with both pinch-off characteristics and current saturation.