Semiconductor Manufacturing Facility Research Articles

Global semiconductor supply chain resilience challenges and mitigation strategies: A novel integrated decomposed fuzzy set Delphi, WINGS and QFD model

The recent COVID-19 pandemic, Ukrainian-Russian conflict, China-US trade war, and current environmental concerns regarding carbon emissions have all made the semiconductor supply chain (SCSC) more vulnerable. In addition, the uncertainty of global SCSC is increasingly obscured owing to several resilience challenges within the exiting supply chain network. Thus, supply chain resilience issues are becoming popular among researchers and policymakers. Unfortunately, there is a lack of systematic research on evaluation of resilience challenges and mitigation strategies for the global SCSC. Additionally, existing models are incompetent to capture the optimistic and pessimistic views of experts during interaction assessment and mitigation strategy evaluation in an uncertain environment. Hence, this research, for the first time, develops a novel integrated Decomposed Fuzzy Set (DFS)-based Delphi, Weighted Influence Non-linear Gauge System (WINGS), and Quality Function Deployment (QFD) model to identify and assess strength-interaction relationship between resilience challenges and mitigation strategies. The findings demonstrated that out of thirteen resilience challenges, seven were identified as causal group resilience challenges while the remaining six were classified as result group resilience challenges indicating that addressing the causal group resilience challenges may directly influence the mitigation of the result group resilience challenges. According to findings of DFS-WINGS analysis, the resilience challenges “Geopolitical tensions” and “Natural disasters” are the two most priority causal group resilience challenges that can significantly influence the result group system components. Furthermore, the DSF-QFD analysis confirmed that the mitigation strategies “Investing in semiconductor R&D and developing regional semiconductor manufacturing facilities” and “Diversification of key components suppliers and promoting domestic manufacturing” received the highest correlation among the mitigation strategies to address the current resilience issues faced by global SCSC. The study findings make a significant contribution to policymaking. The roles of resilience challenges and importance of mitigation strategies both can be used as benchmarks for the SCSC to make the global SCSC more resilient and sustainable.

Novel Materials and Processes for Miniaturization in Semiconductor Packaging

The semiconductor industry is undergoing a significant transformation away from conventional methods of shrinking devices and reducing costs. Chip designers are actively exploring new technological avenues to improve cost-effectiveness while integrating more features into the silicon footprint. One promising strategy is Heterogeneous Integration (HI), which employs advanced packaging techniques to integrate independently designed and manufactured components using the most suitable process technology. However, the adoption of HI brings about design and security challenges. To facilitate HI, it is crucial to advance research and development in advanced packaging.The existing research highlights potential security threats in the advanced packaging supply chain, particularly due to the offshore presence of most Outsourced Semiconductor Assembly and Test (OSAT) facilities/vendors. Addressing the growing demand for semiconductors and ensuring a secure semiconductor supply chain have prompted significant efforts from the United States (US) government to relocate semiconductor fabrication facilities onshore. However, enhancing US-based advanced packaging capabilities is essential to fully realize the vision of establishing a secure, efficient, and resilient semiconductor supply chain. Our endeavor was driven by the need to identify potential bottlenecks and vulnerabilities in the US-based advanced packaging supply chain.

Novel Materials and Processes for Miniaturization in Semiconductor Packaging

The semiconductor industry is undergoing a significant transformation away from conventional methods of shrinking devices and reducing costs. Chip designers are actively exploring new technological avenues to improve cost-effectiveness while integrating more features into the silicon footprint. One promising strategy is Heterogeneous Integration (HI), which employs advanced packaging techniques to integrate independently designed and manufactured components using the most suitable process technology. However, the adoption of HI brings about design and security challenges. To facilitate HI, it is crucial to advance research and development in advanced packaging.The existing research highlights potential security threats in the advanced packaging supply chain, particularly due to the offshore presence of most Outsourced Semiconductor Assembly and Test (OSAT) facilities/vendors. Addressing the growing demand for semiconductors and ensuring a secure semiconductor supply chain have prompted significant efforts from the United States (US) government to relocate semiconductor fabrication facilities onshore. However, enhancing US-based advanced packaging capabilities is essential to fully realize the vision of establishing a secure, efficient, and resilient semiconductor supply chain. Our endeavor was driven by the need to identify potential bottlenecks and vulnerabilities in the US-based advanced packaging supply chain.

Assessment of Occupational Health Risks for Maintenance Work in Fabrication Facilities: Brief Review and Recommendations

BackgroundThis study focuses on assessing occupational risk for the health hazards encountered during maintenance works (MW) in semiconductor fabrication (FAB) facilities. ObjectivesThe objectives of this study include: 1) identifying the primary health hazards during MW in semiconductor FAB facilities; 2) reviewing the methods used in evaluating the likelihood and severity of health hazards through occupational health risk assessment (OHRA); and 3) suggesting variables for the categorization of likelihood of exposures to health hazards and the severity of health effects associated with MW in FAB facilities. MethodsA literature review was undertaken on OHRA methodology and health hazards resulting from MW in FAB facilities. Based on this review, approaches for categorizing the exposure to health hazards and the severity of health effects related to MW were recommended. ResultsMaintenance workers in FAB facilities face exposure to hazards such as debris, machinery entanglement, and airborne particles laden with various chemical components. The level of engineering and administrative control measures is suggested to assess the likelihood of simultaneous chemical and dust exposure. Qualitative key factors for mixed exposure estimation during MW include the presence of safe operational protocols, the use of air-jet machines, the presence and effectiveness of local exhaust ventilation system, chamber post-purge and cooling, and proper respirator use. Using the risk (R) and hazard (H) codes of the Globally Harmonized System alongside carcinogenic, mutagenic, or reprotoxic classifications aid in categorizing health effect severity for OHRA. ConclusionFurther research is needed to apply our proposed variables in OHRA for MW in FAB facilities and subsequently validate the findings.

Controlling For X: Export Controls and Emerging Technology Competition

The prevailing view in Washington is that the United States and China are in a fierce competition for control of critical technologies of the future. The Biden Administration’s October 2022 semiconductor export control rules target China’s ability to make or obtain the most advanced semiconductors – the foundational components of advanced technologies. It is best to understand the United States semiconductor export controls as a tool being wielded by the US government in a fight for global technological dominance, particularly in the realm of AI. This strategy represents a substantial assertion of extraterritorial power by the United States, increases the risk of catastrophic conflict between the United States and China, and has the potential to backfire by accelerating China’s domestic semiconductor industry development. The United States should consider easing elements of the semiconductor export controls in exchange for diplomatic concessions, such as greater bilateral military communication, and focus more attention on increasing domestic production of advanced semiconductor technologies by fast tracking expert visas and permitting for new semiconductor fabrication facilities.

Reduction of Process Chemicals and Energy Use in Single-Wafer Process Applications

The semiconductor industry is a significant consumer of water and chemicals. In particular, water is a valuable resource, and its efficient use is crucial to ensure availability for future generations. By implementing measures to reduce water and chemical consumption, the semiconductor industry can minimize its environmental footprint and contribute to sustainability efforts. Technology for the recycling of unused hot ultrapure water (H-UPW), ozonated water and reclaimed sulfuric acid-hydrogen peroxide mixtures (SPM) has been developed and installed in high-volume manufacturing (HVM) semiconductor manufacturing facilities. This paper presents an overview of the technology and expected savings in water, sulfuric acid and energy consumption from the implementation of these technologies.

Energy advantage of cold energy recovery system using water- and air-side free cooling technologies in semiconductor fabrication plant in summer

The semiconductor industry requires large amounts of energy. Of the total energy, semiconductor manufacturing facilities consume the most electricity, where 21–29% of the total energy is used to maintain a clean room environment at a constant temperature and humidity. The energy required for constant temperature and humidity has been developed and applied in various ways, e.g., waste heat recovery technology without a boiler. However, it is highly difficult to obtain the energy required for cooling without operating a chiller unless there is a climatic advantage. Therefore, with the perspective of introducing cold energy recovery system into outdoor air-conditioner, this paper suggests the analysis of the energy-saving effect of the recovery system which recovers wasted cold energy of the exhaust gas from the semiconductor fabrication plant located in high-temperature and humid region. Two systems have been proposed: a water-side free cooling system that recovers cold energy by connecting a cooling tower to exhaust gas, and an air-side free cooling system that recovers cold energy by connecting a membrane energy heat exchanger. When applied to the conventional outdoor air-conditioner after cold energy recovery in both systems, the energy-saving effect was estimated by a simulation program (i.e., engineer equation solver) using a theoretical calculation model. The result showed that the cooling load of the outdoor air-conditioner decreased by 10.2–13.1% and 8.5–11.2% when the water-side free cooling system and air-side free cooling system, respectively, were applied at an exhaust gas temperature of 24–28 °C and a humidity ratio of 0.00733 kg/kg’. However, with the consideration of the power consumed by the cold energy recovery system (i.e., water/air-side free cooling system), actual energy-saving rate was low. Consequently, the head and static pressure designs of the fluid transfer equipment (i.e., pumps and fans) of the cold energy recovery system should be considered with caution when the cold energy recovery system is applied.

Vehicle Look-Ahead Dispatching for Overhead Hoist Transport System in Semiconductor Manufacturing

This article investigates a look-ahead transport dispatching algorithm for the Automated Material Handling System (AMHS) of a semiconductor manufacturing facility. We consider two types of information: the estimated arrival time of upcoming transports of lots and the time required for an occupied vehicle to become idle. A Mixed Integer Linear programming model has been proposed to minimize the assignment (waiting) time of transport missions. Due to the complexity of the problem, three heuristics have been developed and tested on industrial data. The experiment simulation has been conducted by using a simulation model of a real semiconductor factory. The tests have shown the relevance and the effectiveness of the look-ahead dispatching algorithm.

Implementation of overall equipment effectiveness and financial performance assessment framework in a semiconductor manufacturing facility: A case study

Implementation of overall equipment effectiveness and financial performance assessment framework in a semiconductor manufacturing facility: A case study

Optimizing multiple qualifications of products on non-identical parallel machines

In some manufacturing contexts, such as semiconductor manufacturing, machines must be qualified, or eligible, to process a product, and machines cannot be qualified for all products. This paper investigates the problem of optimizing a given number of new qualifications of products to machines to maximize a flexibility measure that evaluates the balance of the qualification configuration of a work center in terms of utilization rate of machines on a set of non-identical parallel machines. Motivated by empirical observations, new solution approaches, notably inspired by heuristics for discrete location problems and based on the analysis of dual variables, are proposed and compared on industrial data from a semiconductor manufacturing facility and on randomly instances. The use of dual variables leads to heuristics that are effective both in terms of solution quality and computational time. The best proposed approach is currently used in the decision support system of a semiconductor manufacturing facility.

Qubits made by advanced semiconductor manufacturing

Full-scale quantum computers require the integration of millions of qubits, and the potential of using industrial semiconductor manufacturing to meet this need has driven the development of quantum computing in silicon quantum dots. However, fabrication has so far relied on electron-beam lithography and, with a few exceptions, conventional lift-off processes that suffer from low yield and poor uniformity. Here we report quantum dots that are hosted at a 28Si/28SiO2 interface and fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. With this approach, we achieve nanoscale gate patterns with excellent yield. In the multi-electron regime, the quantum dots allow good tunnel barrier control—a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance in the few-electron regime reveals relaxation times of over 1 s at 1 T and coherence times of over 3 ms.

Influence of an R&D lot on productivity in semiconductor manufacturing

Both high productivity of finished goods and new product development are important for manufacturing firms to compete in a market successfully. High productivity is closely related to near-term profit, while new product development is imperative for long-term competitiveness. In a semiconductor fabrication facility, the final stage of new product development is testing new R&D lots in a real mass production environment. Because the test shares the same facility of mass production, if the R&D lots are processed to prioritize fast product development, it negatively influences the productivity of the lines. This study develops a stochastic model to analyze how the flow speed of R&D lots affects starvation of a bottleneck stage and the throughput of regular production lots on a semiconductor fabrication line. The model calculates the distributions of the delay time of R&D lots and the starvation time of the bottleneck stage under a given flow control policy of the R&D lots. Numerical examples are provided to illustrate how this model can be used on actual manufacturing lines to determine appropriate speeds of R&D lots.

Ionizers as Major ESD Countermeasure in 12nm Gate Oxide Semiconductor Manufacturing

The sensitive Electrostatic Discharge (ESD) has been found to be the major causes in semiconductor manufacturing that contributed in the event when the samples did not function properly and failed during testing. Various techniques had been studied and implemented as the ESD countermeasures. Based on the EDS event model, control measures on people, grounding and ionizations have been practiced as the main preventive measures against ESD. However, many aspects of the measures need to be customized to the specific fabrication areas. This paper conducted several experiments in the use of ionizers to tackle the ESD issue in a 12nm Gate Oxide semiconductor fabrication facility. Based on several hypotheses on the areas and operations that are prone to ESD during the back-end processes, experiments were conducted to evaluate them. The results affirm the need to individually and specifically check the effectiveness of the usage of ionizers to combat ESD as some ionizer were found to be not effective at the location or area where they are installed.

Alarm Activations Analysis for Performance Enhancement in a Semiconductor Facility

The performance improvement of alarm systems helps enhance control, operator effectiveness, facility up-times, safety, and eventually reduce losses. During the facility's operation, a large amount of alarm system data are collected and historized. Valuable information can be extracted from the alarms history and used to enrich the facility's control and performance, which prompted the development of alarm management methods and resulted in a need to transform such information into useful visual forms. These visual forms need to help facility operators and engineers understand alarm system behavior and facilitate decision making. This paper presents a framework to monitor and evaluate the alarm system's performance in a semiconductor manufacturing facility. We provide a mathematical formulation of elaborated calculations in this context. We also demonstrate the proposed framework's effectiveness using a real dataset issued from the ST-Rousset semiconductor manufacturing facility.

Z80—The 1970s Microprocessor Still Alive

Reports on the history, development, and applications supported by Zilog Z80 microprocessor. The history of Zilog Z80 is fascinating. According to reliable sources,1 in late 1974, Federico Faggin, who was then best known as the designer of the first commercial microprocessor Intel 4004, and Ralph Ungermann, from the Intel 8080 team, left Intel to form their own company. Then, Masatoshi Shima, who was the transistor-level designer of Intel 8080, left Intel in April 1975 to join Faggin and Ungermann. At the beginning, Faggin intended to develop a single-chip computer (microcontroller), but soon realized that it is difficult to compete in the microcontroller market with a company who has its own semiconductor fabrication facility. In December 1975, Faggin came up with an idea of developing a 5-V microprocessor, which was machine core compatible with then popular Intel 8080, and adding most of the functionalities available in Motorola 6800, so that they could pinch both markets. Faggin, Ungermann, and Shima managed to find a venture capital from Exxon Enterprises for the development of a new microprocessor Z80 and formed their own company Zilog.

Job scheduling of diffusion furnaces in semiconductor fabrication facilities

Furnaces are commonly seen in the front-end to the middle portion of the semiconductor process flow and their scheduling plays a key role in semiconductor manufacturing. Job scheduling of furnaces needs to meet the daily production targets while adhering to job due dates and process constraints. The furnace scheduling problem belongs to a special class of flexible job-shop scheduling with complicated constraints including but not limited to batch processing, reentrance, and time-windows. This problem is NP-hard. The extremely large solution space prevents any straightforward application of optimization techniques. In this paper, several properties are identified to reduce the solution space based on a dynamic programming formulation. With the help of these properties, an efficient algorithm has been developed to find a good solution to this problem. The developed method has been implemented in practical production lines. Compared with existing methods, the developed algorithm gives a higher throughput rate and improves the scheduling efficiency.

Optimizing the energy efficiency of chiller systems in the semiconductor industry through big data analytics and an empirical study

Big data analytics is playing a more and more prominent role in the manufacturing industry as corporations attempt to utilize vast amounts of data to optimize the operation of plants and factories to gain a competitive advantage. Since the advent of Industry 4.0, also known as smart manufacturing, big data analytics, combined with expert domain knowledge, is facilitating ever-greater levels of speed and automaticity in manufacturing processes. The semiconductor industry is a fundamental driver of this transformation; moreover, due to the highly complex and energy-consuming nature of the semiconductor manufacturing process, semiconductor fabrication facilities (fabs) can also benefit greatly from incorporating big data analytics to improve production and energy efficiency. This paper developed a big data analytics framework, along with an empirical study conducted in collaboration with a semiconductor manufacturer in Taiwan, to optimize the energy efficiency of chiller systems in semiconductor fabs. Chiller systems are one of the most energy-consuming systems within a typical modern fab. The developed big data analytics framework allows production managers to ensure that chiller systems operate at an optimized level of energy efficiency under dynamically changing conditions, while fulfilling the chilling demands. Compared to the commonly-used heuristics previously employed at the fab to tune chiller system parameters, by the utilization of big data analytics, it is shown that fabs can achieve substantial energy savings, greater than 12%. The developed framework and the lessons learned from the empirical study are not only generalizable but also useful for practitioners who are interested in applying big data analytics to optimize the performance of other equipment systems in fabs.

Treatment of Azole-Containing Industrial Wastewater by the Fenton Process

Some semiconductor fabrication processes generate high-strength wastewater that may contain high concentrations of azoles, amines, hydrogen peroxide, organic, and inorganic co-contaminants, making the treatment of this wastewater challenging. In this study, the Fenton process was utilized for the treatment of 53 mM pyrazole and 34 mM 2-(2-aminoethoxy) ethanol (known as diglycolamine, DGA) in a lab-prepared aqueous mixture containing 3.5 M hydrogen peroxide and 16 mM inorganic fluoride. The effects of operational variables for the Fenton process, such as temperature (10, 18, or 25 °C), iron dosing (32.3, 37.3, or 74.5 mM), and pH (2.5, 3.0, or 3.5), on the degradation rates were investigated. The chosen variables were then used to treat wastewater from a semiconductor fabrication facility. The Fenton process was effective in treating both the lab-prepared mixture and semiconductor industrial wastewater. The degradation of pyrazole and DGA yielded a range of byproducts including inorganic ions and organic acids.

Photochemical fate of sulfonium photoacid generator cations under photolithography relevant UV irradiation

Onium salts, widely used as photoacid generators (PAGs) in the semiconductor industry, are receiving increased regulatory scrutiny due to their potential hazardous properties. Evaluating the environmental impacts of these chemicals requires knowledge of the fate of the onium species during photolithography steps, which remains unclear for many PAGs. The current study investigated the fate of four representative sulfonium PAGs using an irradiation setup simulating industrial photolithography. The photolytic fate for three of the four selected onium cations is reported for the first time. All onium compounds reacted rapidly under 254 nm irradiation, and their half-lives ranged from 51 to 214 s with high quantum yields (0.23−0.85). Multiple highly aromatic and hydrophobic photoproducts were characterized using HPLC-DAD and GC-MS; eight PAG photoproducts were identified for the first time. Authentic commercial standards of some of the photoproducts were available, enabling quantitative estimates of recoveries. The molar recovery of aromatic rings based on these quantified photoproducts was in the range of 4.9–71.4 %. A homolytic reaction mechanisms is proposed and discussed. The results provide insight on the potential environmental impact pertinent to the use of PAGs, e.g., prediction of residual onium levels and the identity of photoproducts in effluents from semiconductor fabrication facilities.

반도체 FAB에서 웨이퍼 로트 적기운반을 위한 재공 저장 위치 선정 연구

This paper proposes a work-in-process (WIP) allocation approach to improve on-time transfers of a unified automated material handling system (AMHS) in a semiconductor fabrication facility (FAB). The real-time operation and control of the complex AMHS often cause delayed transfers of wafers to manufacturing machines and result in production loss. We introduce transfer-due-dates from storages to manufacturing machines to enhance the on-time transfers in the AMHS and develop a mathematical model to allocate the WIP to the optimized storage locations based on transfer- due-date. The simulation results demonstrate that the machine utilization as well as the AMHS capability for on-time transfers can be improved by assigning the wafers’ interim storage locations more appropriately.