Abstract

Both high productivity of finished goods and new product development are important for manufacturing firms to compete in a market successfully. High productivity is closely related to near-term profit, while new product development is imperative for long-term competitiveness. In a semiconductor fabrication facility, the final stage of new product development is testing new R&D lots in a real mass production environment. Because the test shares the same facility of mass production, if the R&D lots are processed to prioritize fast product development, it negatively influences the productivity of the lines. This study develops a stochastic model to analyze how the flow speed of R&D lots affects starvation of a bottleneck stage and the throughput of regular production lots on a semiconductor fabrication line. The model calculates the distributions of the delay time of R&D lots and the starvation time of the bottleneck stage under a given flow control policy of the R&D lots. Numerical examples are provided to illustrate how this model can be used on actual manufacturing lines to determine appropriate speeds of R&D lots.

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