Testing Of Semiconductor Devices Research Articles

Simulation of space heavy-ion induced primary knock-on atoms in bipolar devices

Bipolar junction transistors (BJTs) are often used in spacecraft due to their excellent working characteristics. However, the complex space radiation environment induces primary knock-on atoms (PKAs) in BJTs through collisions, resulting in hard-to-recover displacement damage and affecting the performance of electronic components. In this paper, the properties of PKAs induced by typical space heavy ions (C, N, O, Fe) in BJTs are investigated using Monte Carlo simulations. The simulated results show that the energy spectrum of ion-induced PKAs is primarily concentrated in the low-energy range (17 eV–100 eV) and displays similar features across all tested ions. The PKAs induced by the collision of energetic ions have large forward scattering angles, mainly around 88°. Moreover, the distribution of PKAs within a transistor as a function of depth displays a peak characteristic, and the peak position is linearly proportional to the incident energy at a certain energy range. These simulation outcomes serve as crucial theoretical support for long-term semiconductor material defect evolution and ground testing of semiconductor devices.

Accelerated Testing of High Power Transistors for Long Operation when Solving Problems of Prediction of their Reliability by the Method of Imitation Simulation

When evaluating the individual reliability of semiconductor devices by gradual failures for a given operating time, the value of the electrical parameter of a particular instance for this operating time is predicted using the simulation method. To obtain a prediction of an electrical parameter, it is necessary to have a simulation model in the form of a function of the relationship between a given operating time and the level of simulation impact. The simulation model is obtained with the help of preliminary studies (training experiment) of a training sample of semiconductor devices of the type of interest with the volume of approximately 50 ... 100 copies. The application of the model is reduced to the calculation of the level of simulation impact corresponding to a given operating time. The result of measuring the electrical parameter at the calculated level of the imitation impact in a new specimen of the same type that did not take part in the training experiment should be considered as a prediction of this parameter for a given operating time. An integral part of the preliminary research to obtain a simulation model is the testing of semiconductor devices of the training set for a long operating time, which can be tens of thousands of hours, which necessitates planning and conducting accelerated tests. The article substantiates the conditions for conducting accelerated forced tests in relation to high-power bipolar transistors of the KT872A type. The increased temperature and the reverse voltage applied to the collector junction of the transistors are chosen as factors accelerating the tests. The test acceleration coefficient is calculated relative to the operating mode of the transistors. Based on the results of the accelerated tests for the electrical parameter (collector-emitter saturation voltage), a mathematical model was obtained in the form of a dependence of its average value on the operating time. The presence of this model is necessary to determine the function of recalculating the given operating time of transistors to the value of the simulation impact.

Framework for TCAD augmented machine learning on multi- I–V characteristics using convolutional neural network and multiprocessing

In a world where data is increasingly important for making breakthroughs, microelectronics is a field where data is sparse and hard to acquire. Only a few entities have the infrastructure that is required to automate the fabrication and testing of semiconductor devices. This infrastructure is crucial for generating sufficient data for the use of new information technologies. This situation generates a cleavage between most of the researchers and the industry. To address this issue, this paper will introduce a widely applicable approach for creating custom datasets using simulation tools and parallel computing. The multi-I–V curves that we obtained were processed simultaneously using convolutional neural networks, which gave us the ability to predict a full set of device characteristics with a single inference. We prove the potential of this approach through two concrete examples of useful deep learning models that were trained using the generated data. We believe that this work can act as a bridge between the state-of-the-art of data-driven methods and more classical semiconductor research, such as device engineering, yield engineering or process monitoring. Moreover, this research gives the opportunity to anybody to start experimenting with deep neural networks and machine learning in the field of microelectronics, without the need for expensive experimentation infrastructure.

Agile development technology of test application program suitable for semiconductor device testing

The semiconductor devices (especially integrated circuits/chips) test field involves a wide range of device types and test parameters, which leads to low development efficiency, poor stability, weak reuse, long development cycle and repetitive work in application development. Therefore, a test application development method based on reusable component technology is proposed in this paper. Firstly, this paper introduces the basic concepts and characteristics of the reusable component technology. Then, according to the current situation of semiconductor device testing, the design method of component-based test application program is described. Finally, the typical semiconductor device test application program is designed and developed by using LabWindows/CVI integrated development environment. Practice has proved that the component-based test application program design can speed up the R&D and ensure the software quality at the same time. The agile development requirement of application program for semiconductor device test system can be satisfied.

Characterization Circuit, Gate Driver and Fixture for Wide-Bandgap Power Semiconductor Device Testing

The world is currently experiencing major advancement in the electrification of both the industrial and commercial sectors. This is part of an effort to reduce reliance on combustible fuels, reduce emissions, integrate renewable energy systems and increase efficiency. Due to the complexity of modern circuits and systems, any circuit’s design should start with proper simulation and device selection, to reduce overall cost and time of prototyping, both of which require accurate and thorough device characterization. Wide bandgap (WBG) power semiconductor devices offer superior characteristics over conventional devices, including faster switching speeds, higher breakdown voltage, lower losses, and higher operating temperature. These properties call for special test circuits and procedures for accurate characterization. In this work, custom characterization circuits and fixtures, suitable for WBG devices are designed, tested, and described. The circuits measure several of the main characteristics of voltage controlled WBG power switches. Different technology devices were tested and characterized.

Los Alamos High-Energy Neutron Testing Handbook

<div class="section abstract"><div class="htmlview paragraph">The purpose of the Los Alamos High-Energy Neutron Testing Handbook is to provide user information and guidelines for testing Integrated Circuits (IC) and electronic systems at the Irradiation of Chips and Electronics (ICE) Houses at the Los Alamos Neutron Science Center (LANSCE) at Los Alamos National Laboratory (LANL). Microelectronic technology is constantly advancing to higher density, faster devices and lower voltages. These factors may increase device susceptibility to radiation effects. The high-energy neutron source at LANSCE/LANL provides the capability for accelerated neutron testing of semiconductor devices and electronic systems and to simulate effects in various neutron environments.</div></div>

Focus on test, measurement, and data acquisition

Focus on test, measurement, and data acquisition

Optimization of pick-and-place in die attach process using a genetic algorithm

The entire semiconductor manufacturing process can be largely divided into two sequential sub-processes that are commonly referred to as front-end and back-end production. Both production processes involve many complicated and elaborate steps for wafer fabrication, probe testing and sorting, assembly, final test, etc. The front-end process refers to wafer fabrication process, whereas the back-end process refers to the assembly, packaging, and testing of individual semiconductor devices. Once the front-end process is complete, the wafers are transferred to the back-end process in order to facilitate its integration into electronic devices and to take final performance test. In back-end production process, based on quality and location information of individual chip (die) derived from the EDS process, only good semiconductor chips (dies) are individually picked up by an automatic robot arm and then attached to the support structure (e.g., the lead frame) on a strip. This process is called die attach process. In order to improve the production efficiency of die attach process, it is necessary to evaluate various robot arm operation methods (rules) and then to provide the most efficient operation method since the total transfer distance (or total transfer time) considerably depends on the robot arm operation methods as well as the distribution of good chips on wafers. Thus, in this research, a pick-and-place problem of the die attach process is mathematically formulated and several transfer methods are compared.

Thermal Analysis of Power Thyristor Used in ITER Poloidal Field Converter

As a key component of ITER PF converter module, thyristor conducting large current produces a lot of power loss, therefore it is meaningful to study its heat transfer characteristic for improving the performance of PF converter. This paper presents the thermal analysis of the thyristor. A 3D finite-element model with multi material layers is built and simulated in steady state operation. A special temperature rise test scheme is designed and done to verify the analysis result. The simulation is well in compliance with the test result. The modeling method presented in this paper is proved to be practical in thyristor thermal analysis. The proposed measurement method in temperature rise test is also of valuable reference for thermal testing of power semiconductor devices.

Capacitive methods for testing of power semiconductor devices

Electrical capacity of power semiconductor devices is quite an important parameter that can be utilized not only for testing a component itself, but it can also be applied practically; e.g. in series-connected high voltage devices. This paper first analyzes the theoretical voltage distribution on the bases of the polarized p-n junction, as well as the size of capacity. The measurement of the voltage-capacity dependence using the resonance principle is illustrated on the samples of 4kV and 6kV thyristors. The correspondence between theoretical estimation of the capacity, measured voltage capacity dependence based on the resonance principle and experimentally determined by injected charge proves the correctness of the applied procedures and assumptions.

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

Web Service Based Process for Dynamic Manufacturing

Manufacturing system has changing their technology to service based application. In the contents, web service technique can be a solution for their needs. Web service can provide various business logic, process, application for manufacturing system’s software over the internet. In this paper, we propose web service based process model for manufacturing system. The sample target system is IC test Handler, semiconductor device test equipment. The main application consists of 4 services; operational process, GPIB test process, Communication process, and Data management process.

Wafer Test Methods to Improve Semiconductor Die Reliability

Incremental advances in semiconductor device testing have improved device quality and reliability. New test methods applied to dies at the wafer level are now significantly improving the reliability of devices sold to the increasing bare-die market and reducing burn-in requirements for packaged devices.

On Steepest-Descent-Kaczmarz methods for regularizing systems of nonlinear ill-posed equations

We investigate modified steepest-descent methods coupled with a loping Kaczmarz strategy for obtaining stable solutions of nonlinear systems of ill-posed operator equations. We show that the proposed method is a convergent regularization method. Numerical tests are presented for a linear problem related to photoacoustic tomography and a nonlinear problem related to the testing of semiconductor devices.

In-house development of scheduling decision support systems: case study for scheduling semiconductor device test operations

Most manufacturing processes can benefit from an automated scheduling system. However, the design of a fast, computerised scheduling system that achieves high-quality results and requires minimal resources is a difficult undertaking. Efficient scheduling of a semiconductor device test facility requires an information system that provides good schedules quickly. Semiconductor device testing is the last stage of the long semiconductor manufacturing process, and therefore is subjected to customer service pressures. The cost of an off-the-shelf computerised scheduling system may be prohibitive for many companies. In addition, many companies are taken aback by other characteristics of off-the-shelf scheduling systems, such as code confidentiality, maintenance costs, and failure rates. We draw upon the literature and our field case to discuss some of the trade-offs between in-house development and off-the-shelf acquisition of software. We describe the in-house design and implementation of a scheduling decision support system for one device test facility. Using the design and implementation process of this system as a case study, we discuss how one facility uses in-house design of systems in a strategic way, as a competitive capability.

Integrating Semiconductor Device Characterisation and Reliability into Electrical Engineering Education

Semiconductor device reliability physics and testing have been successfully integrated into a semiconductor device fabrication course as supplementary contents, to embody more comprehensively the challenges and concerns of the semiconductor industry. In the semiconductor device fabrication class, students are exposed not only to the theory of basic processing techniques of integrated circuit fabrication, but also to the reliability issues arising from device scaling, such as hot carrier effect and time-dependent dielectric breakdown in MOS transistors. By adding reliability theory and testing, students will find the course more interesting and stimulating. They not only grasp measurement techniques, but also gain insight into device reliability. This helps them for job hunting or pursuing advanced education or research.

Using the LANSCE irradiation facility to predict the number of fatal soft errors in one of the world’s fastest supercomputers

Los Alamos National Laboratory (LANL) is home to the Los Alamos Neutron Science Center (LANSCE). LANSCE is a unique facility because its neutron spectrum closely mimics the neutron spectrum at terrestrial and aircraft altitudes, but is many times more intense. Thus, LANSCE provides an ideal setting for accelerated testing of semiconductor and other devices that are susceptible to cosmic ray induced neutrons. Many industrial companies use LANSCE to estimate device susceptibility to cosmic ray induced neutrons, and it has also been used to test parts from one of LANL’s supercomputers, the ASC (Advanced Simulation and Computing Program) Q. This paper discusses our use of the LANSCE facility to study components in Q including a comparison with failure data from Q.

High-Temperature RF Probe Station for Device Characterization Through 500<tex>$^circ$</tex>C and 50 GHz

A high-temperature measurement system capable of performing on-wafer microwave testing of semiconductor devices has been developed. This high-temperature probe station can characterize active and passive devices and circuits at temperatures ranging from room temperature to above 500/spl deg/C. The heating system uses a ceramic heater mounted on an insulating block of NASA Shuttle tile. The temperature is adjusted by a graphical computer interface and is controlled by the software-based feedback loop. The system is used with a vector network analyzer to measure scattering parameters over a frequency range from 1 to 50 GHz. The microwave probes, cables, and inspection microscope are all shielded to protect from heat damage. The high-temperature probe station has been successfully used to characterize gold transmission lines on silicon carbide at temperatures up to 540/spl deg/C.

Semiconductor test strategies

The test industry is currently looking for innovative solutions to address both the rising cost of testing and the growing influence that testing has on the time-to-market for new devices. These solutions include new tester technologies, new test practices and strategies, and increasing the output, experience level, and motivation of test engineers. With this in mind, this article presents a brief background on semiconductor device testing, an overview of the current issues that test engineers are facing and some of the strategies being used to overcome the rising cost of semiconductor device testing.

DUV Microscopy for Wafer and Mask Inspection and Metrology

Abstract This article provides an overview of deep ultraviolet (DUV) microscopy, the factors that led to its development, and the types of applications for which it is suited in semiconductor device manufacturing, testing, and inspection. It also includes several images demonstrating it capabilities relative to visible light microscopy.