Semiconductor Capacitors Research Articles

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer.

In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10−6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm−2 eV−1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77–227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future.

Unraveling the Mechanism of Remote Scavenging Effect at the InP/Al2O3 Interface Induced by Titanium Layer

AbstractLow interface oxide concentration is desired for III‐V semiconductor/high k dielectrics stacks to get high‐performance devices. The remote scavenging effect is observed upon Ti metal deposition on the InP/Al2O3 system, characterized by in situ angle resolved X‐ray photoelectron spectroscopy and time‐of‐flight secondary ion mass spectrometry, as well as ex situ cross‐sectional transmission electron microscopy. The mechanism is investigated by O18 tracing. Two mechanisms are proposed for this remote scavenging effect. The impact of this remote scavenging effect is studied by metal oxide semiconductor (MOS) capacitors fabrication and characterization. This work sheds light on InP‐based MOS devices.

Extraction of dipolar coupling constants from low-frequency electrically detected magnetic resonance and near-zero field magnetoresistance spectra via least squares fitting to models developed from the stochastic quantum Liouville equation

We report low-frequency electrically detected magnetic resonance (EDMR) and near-zero field magnetoresistance (NZFMR) measurements observed through spin-dependent trap-assisted tunneling on unpassivated 28Si/28SiO2 metal–insulator–semiconductor (MIS) capacitors. This study both experimentally and theoretically explores the effects of the low-frequency EDMR response and the mechanisms responsible for spin-mixing, which leads to the NZFMR response in the absence of electron–nuclear hyperfine interactions. Previous reports that utilized high-frequency EDMR and NZFMR on these devices indicated that the observed trap-assisted tunneling spectra are dominated by silicon dangling bonds back bonded to silicon at the Si/SiO2 interface, Pb0 and Pb1 centers. These previous results also suggest that the rate limiting step in trap-assisted tunneling is the interface to an oxide trapping event. In this work, we extend the theory to show the explicit connection of the defects observed between the NZFMR response and the EDMR, which has not yet been demonstrated. We also extend a theoretical approach to the analysis of both the EDMR and NZFMR spectra and match the theory to experimental observations made in 28Si/28SiO2 MIS capacitors. The method utilizes a least squares fitting algorithm of models developed from the stochastic quantum Liouville equation. We find that we can extract a dipolar coupling constant by fitting both the NZFMR and EDMR spectra. Our experimental results and resulting fitted spectra from our quantitative model suggest the mechanism responsible for spin-mixing, which leads to the NZFMR response in the absence of electron–nuclear hyperfine interactions, is predominately magnetic dipolar interactions between Pb centers at the interface.

Synergistic effects in MOS capacitors with an Au/HfO2–SiO2/Si structure irradiated with neutron and gamma ray

The properties of oxide trapped charges and interface state density in the metal oxide semiconductor (MOS) capacitors with an Au/HfO2–SiO2/Si structure were investigated under irradiation of 14 MeV neutron and 60Co gamma-ray. In the mixed neutron and gamma irradiation environment, the formation of the oxide trapped charges in the HfO2–SiO2 layer is determined by the total deposited ionization energy, i.e. the sum of ionization energy deposition of the neutrons and the accompanying gamma rays, while the influence of the displacement damage caused by 14 MeV neutrons can be ignored. The interface state density depends not only on the ionizing energy loss (IEL) but also the non-IEL (NIEL), and NIEL plays a major role below the critical neutron fluence of 4.5 × 1012 n cm−2. The synergistic effect of the interface state is observed increases with energy deposition in the oxide at lower fluences, while decreasing above the critical fluence. These results confirm the existence of the synergistic effect of neutron and gamma irradiation in damaging HfO2 MOS devices.

Radio frequency power controlled [formula omitted] crystal phase transition from monoclinic to cubic

Rare earth oxides such as Gadolinia (Gd2O3) are extensively explored for buried oxide (BOX) application as a replacement for silicon dioxide (SiO2) in silicon-on-insulator (SOI) substrates. Of all the proposed methods, molecular-beam-epitaxy-based techniques have shown perfectly single-crystalline growth of Gd2O3. We present a radio frequency (RF) magnetron sputter based low-cost technique to grow single-crystalline Gd2O3 on Si (111) substrate. We show a gradual phase transition of the Gd2O3 layer from monoclinic to cubic by engineering the Gd2O3 deposition rate–i.e., tuning the RF power. We present a comparison amongst three samples as follows: (a) monoclinic; (b) monoclinic+cubic; (c) cubic at three different RF powers keeping the rest of the process conditions such as chamber pressure, Argon flow rate, etc., fixed. Further, we present a detailed structural characterization of all the three samples using a high-resolution X-ray diffraction system. Using the ω−2θ and pole-figure measurements we show a highly textured monoclinic Gd2O3 layer formation with (-402) crystal orientation in experiment (a). In experiment (c) we show phase transition of Gd2O3 from monoclinic to cubic by tuning the RF power. Finally, with experiment (b), we demonstrate that the aforementioned phase transition is a gradual phenomenon by highlighting a coexistence of both the monoclinic and cubic phases at an intermediate RF power. To ensure the electrical characteristics of the grown dielectric we present a metal oxide semiconductor capacitor structure fabrication for the monoclinic and the cubic Gd2O3 layers and benchmark the interface trap density, and dielectric constant against state-of-the-art literature. We show an improvement in the interface trap density, and reduction in the hysteresis from monoclinic to cubic phase transition due to an improved epitaxial relation between cubic Gd2O3 and Si(111) substrate. Such low-cost methods of growing single-crystalline Gd2O3 layer has the potential to replace the SiO2 BOX layer, and significantly bring down the manufacturing cost of the existing SOI wafer technology.

Investigation of degradation mechanism after negative bias temperature stress in Si/SiGe channel metal–oxide–semiconductor capacitors induced by hydrogen diffusion

In this research, based on I–V and C–V measurement at different temperatures, the interface defect density in the device with the Si/SiGe channel was discussed. In addition, negative bias temperature instability (NBTI) is also studied. In previous research, most of the flat-band voltage (V FB) shifts during NBTI stress was attributed to hole injection. In this article, however, the release of atomic hydrogen from the Si–H bonds at the SiO2/Si interface and at the SiGe interface produces a fixed oxide charge, which causes V FB shifts which vary with material.

Transport mechanism in O-terminated diamond/ZrO2 based MOSCAPs

Metal Oxide Semiconductor capacitors were fabricated using p-type O-terminated (001) diamond and zirconium dioxide deposited by atomic layer deposition at low temperature (100 °C). X-ray diffraction and transmission electron microscopy evidence monoclinic structure and polycrystalline nature of the oxide layer. I-V, CV and CF experiments have been performed in a large frequency range, i.e. from 1 Hz to 1 MHz, in order to analyse the electrical properties of the metal/dielectric/diamond stack. The presence of charges in the oxide and interface states induces a flat-band voltage shift in the CV curve and a strong Fermi level pinning effect. A leakage current mechanism considering the correlation of the microstructural characterization and the electrical response is proposed.

Large-scale and energy-efficient tensorized optical neural networks on III–V-on-silicon MOSCAP platform

This paper proposes a large-scale, energy-efficient, high-throughput, and compact tensorized optical neural network (TONN) exploiting the tensor-train decomposition architecture on an integrated III–V-on-silicon metal–oxide–semiconductor capacitor (MOSCAP) platform. The proposed TONN architecture is scalable to 1024 × 1024 synapses and beyond, which is extremely difficult for conventional integrated ONN architectures by using cascaded multi-wavelength small-radix (e.g., 8 × 8) tensor cores. Simulation experiments show that the proposed TONN uses 79× fewer Mach–Zehnder interferometers (MZIs) and 5.2× fewer cascaded stages of MZIs compared with the conventional ONN while maintaining a >95% training accuracy for Modified National Institute of Standards and Technology handwritten digit classification tasks. Furthermore, with the proven heterogeneous III–V-on-silicon MOSCAP platform, our proposed TONN can improve the footprint-energy efficiency by a factor of 1.4 × 104 compared with digital electronics artificial neural network (ANN) hardware and a factor of 2.9 × 102 compared with silicon photonic and phase-change material technologies. Thus, this paper points out the road map of implementing large-scale ONNs with a similar number of synapses and superior energy efficiency compared to electronic ANNs.

Influence of substrate temperature on optical, structural and dielectric properties of TiO2 thin films prepared by spray pyrolysis technique

Titanium dioxide (TiO2) thin films are prepared on various substrates like glass and silicon wafers by spray pyrolysis method. The spray solution is prepared by dissolving titanium-tetra isopropoxide (TTIP) in ethanol. Optical, structural and dielectric properties of these films are studied by the transmittance spectra, X-ray diffraction (XRD), atomic force microscopy (AFM), capacitance–voltage (C-V) characteristics, respectively. TiO2 metal oxide semiconductor (MOS) capacitors are fabricated using TiO2 as a dielectric medium. C-V plots are analyzed to determine the dielectric constant (εr) of TiO2 film. The dependance of εr of the TiO2 films with the substrate temperature has been investigated.

Investigation of the Intrinsic Nature of Organic Semiconductors Using a Metal Contact-Induced Capacitance Study in Organic Metal–Insulator–Semiconductor Capacitors

Investigation of the Intrinsic Nature of Organic Semiconductors Using a Metal Contact-Induced Capacitance Study in Organic Metal–Insulator–Semiconductor Capacitors

Impact of ZrO2 Dielectrics Thickness on Electrical Performance of TiO2 Thin Film Transistors with Sub-2 V Operation

In the present work, the impact of ZrO2 gate dielectric thickness on the electrical performance of TiO2 thin film transistors (TFTs) is systematically investigated. Exhaustive electrical measurements on TFTs, metal–insulator–metal, and metal–oxide–semiconductor capacitors are carried out with varying ZrO2 dielectrics of different thicknesses. It is found that the ZrO2 possesses an outstanding thickness scalability, providing reliable dielectric properties under an ultrathin physical thickness of 5 nm, while further reduction in ZrO2 thickness would lead to a breakdown of the TFTs, indicating the physical limitations for the ultrathin ZrO2 dielectrics. The TiO2 TFTs with the 5 nm-thick ZrO2 dielectric exhibit an enhanced electrical performance, including a high on/off current ratio (Ion/Ioff) of 7.7 × 108, a nearly ideal subthreshold (SS) of 72 mV/dec, and a high electron mobility (μeff) of 5.74 cm2·V–1·s–1 under an ultralow voltage of 2 V. Such prominent electrical characteristics with a battery-drivable low-voltage operation prove the suitability of the TiO2 TFTs for Internet of Things applications. This comprehensive study, revealing the behaviors of leakage current, oxide capacitance, oxide charges, and interface traps with respect to the ZrO2 thickness, sheds light on the quality and scalability of the ZrO2 dielectrics that can be extended to other channel materials, and also offers a framework for evaluating the material quality of other dielectrics. Furthermore, from a material point of view, the underlying physical reasons for the excellent ZrO2 thickness scalability are believed to be (1) the smooth surfaces of TiO2 and ZrO2, (2) the well-structured ZrO2 without detectable oxygen-related defects, and (3) the large conduction band offset between ZrO2 and TiO2. Overall, this study not only shows that the TiO2 TFTs hold great potential to empower future IoT applications, but also provides important guidance regarding dielectric scaling and quality evaluation in the nanometer scale.

Effect of an inserted Al2O3 passivation layer for atomic layer deposited HfO2 on indium phosphide

In this study, we demonstrate indium phosphide (InP) metal–oxide–semiconductor capacitors (MOSCAPs) with single HfO2 and stacked HfO2/Al2O3 dielectrics. Based on these capacitors, the effect of an inserted Al2O3 passivation layer with various thicknesses on the properties of InP MOSCAPs was further statistically investigated. By inserting a 2 nm thick Al2O3 passivation layer between high-κ HfO2 and the InP substrate, the characteristics including the frequency dispersion, leakage current and interface trap density (D it) were effectively improved, which could be attributed to the large bandgap of Al2O3 that suppressed substrate element diffusion and reduced oxidation of the InP substrate. A low D it of ∼3.8 × 1011 cm−2 eV−1 that was comparable to that of previously reported InP MOSCAPs was achieved. However, with the thickness of Al2O3 decreasing from 2 to 1 nm, the frequency dispersion and D it were slightly increased, because such an ultrathin Al2O3 layer could not effectively suppress the diffusion and may induce substrate oxidation after annealing. The present results show that the incorporation of an Al2O3 passivation layer with suitable thickness has great promise in future high-performance InP device applications.

Effects of 29Si and 1H on the near-zero field magnetoresistance response of Si/SiO2 interface states: Implications for oxide tunneling currents

We report on a study that offers fundamental physical insight into an important phenomenon in solid state device physics, tunneling in Si/SiO2. We observe near-zero field magnetoresistance via spin-dependent trap-assisted-tunneling in both unpassivated and passivated Si/SiO2 and 28Si/28SiO2 metal–insulator–semiconductor (MIS) capacitors. A previous report, which utilized electrically detected magnetic resonance and NZFMR on these devices, indicates a surprising conclusion: the observed trap-assisted tunneling spectra are dominated by silicon dangling bonds back bonded to silicon at the Si/SiO2 interface, Pb0 and Pb1 centers. In this study, the four sets of samples are virtually identical, apart from the presence or absence of either 1H and 29Si. We observed a substantial narrowing of the NZFMR response with the removal of 29Si nuclei and a substantial broadening with the addition of 1H. Since superhyperfine interactions between 29Si nuclei Pb at the Si/SiO2 interface are a full order of magnitude stronger than such interactions involving silicon dangling bonds defects (E′ centers) within the oxide, the NZFMR results strongly suggest a response dominated by Si/SiO2 interface trap defects. With the introduction of 1H magnetic nuclei to the interface after a forming gas anneal, linewidths and lines shapes of Si/SiO2 and 28Si/28SiO2 MIS capacitors were nearly identical. However, the amplitude of the NZFMR response is greatly reduced by the introduction of hydrogen by a fraction about equal to the reduction in the interface trap density. Our results further indicate that the rate limiting step in trap-assisted tunneling is the interface to oxide trapping event.

Characteristics of In0.7Ga0.3As MOS Capacitors with Sulfur and Hydrazine Pretreatments

This paper proposes an effective pretreatment process that combines wet ammonium sulfide ((NH4)2S) dipping and hydrazine (N2H4) vapor treatment before high dielectric constant (κ, kappa) deposition to reduce native oxide and elemental arsenic (As) before atomic layer deposition of ammonium oxide (Al2O3) gate dielectrics on n-doped indium gallium arsenide (In0.7Ga0.3As) layers to form metal oxide semiconductor capacitors (MOSCAPs). X-ray photoelectron spectroscopy (XPS) analysis confirms that sulfuration of In0.7Ga0.3As surface by (NH4)2S solution dipping can effectively reduce indium–oxygen (In–O), gallium–oxygen (Ga–O), arsenic–oxygen (As–O) bonds while elemental As still exist at the high-κ/In0.7Ga0.3As interface. Furthermore, N2H4 treatment on sulfurated In0.7Ga0.3As can effectively suppress the native oxides and elemental As. Accordingly, the obtained data indicate that the combination of chemical sulfur pretreatment and N2H4 treatment is advantageous to passivate the trap states on In0.7Ga0.3As metal–oxide–semiconductor capacitors (MOSCAPs). Moreover, forming gas annealing (FGA) process could further improve the capacitance-voltage (C–V) characteristics and the interface trap density (Dit) of In0.7Ga0.3As MOSCAP could be reduced significantly, achieving a value of 1.2 × 1012 cm−2 eV−1.

In Situ Dielectric Al2O3/β‐Ga2O3 Interfaces Grown Using Metal–Organic Chemical Vapor Deposition

AbstractHigh quality dielectric‐semiconductor interfaces are critical for reliable high‐performance transistors. This paper reports the in situ metal–organic chemical vapor deposition of Al2O3 on β‐Ga2O3 as a potentially better alternative to the most commonly used atomic layer deposition (ALD). The growth of Al2O3 is performed in the same reactor as Ga2O3 using trimethylaluminum and O2 as precursors without breaking the vacuum at a growth temperature of 600 °C. The fast and slow near interface traps at the Al2O3/β‐Ga2O3 interface are identified and quantified using stressed capacitance–voltage (CV) measurements on metal oxide semiconductor capacitor (MOSCAP) structures. The density of shallow and deep level initially filled traps (Dit) are measured using ultraviolet‐assisted CV technique. The average Dit for the MOSCAP is determined to be 6.4 × 1011 cm−2eV−1. The conduction band offset of the Al2O3/ Ga2O3 interface is also determined from CV measurements and found out to be 1.7 eV which is in close agreement with the existing literature reports of ALD Al2O3/Ga2O3 interface. The current–voltage characteristics are also analyzed and the average breakdown field is extracted to be approximately 5.8 MV cm−1. This in situ Al2O3 dielectric on β‐Ga2O3 with improved dielectric properties can enable Ga2O3‐based high‐performance devices.

A Resonantly Driven, Electroluminescent Metal Oxide Semiconductor Capacitor with High Power Efficiency.

Electroluminescence can be generated from a wide variety of emissive materials using a simple, generic device structure. In such a device, emissive materials are deposited by various means on a metal oxide semiconductor capacitor structure across which alternating current voltage is applied. However, these devices suffer from low external efficiencies and require the application of high voltages, thus hindering their practical usage and raising questions about the possible efficiencies that can be achieved using alternating current driving schemes in which injection of bipolar charges does not occur simultaneously. We show that appropriately chosen reactive electrical components can be leveraged to generate passive voltage gain across the device, allowing operation at input voltages below 1 V for devices across a range of gate oxide thicknesses. Furthermore, high power efficiencies are observed when using thermally activated delayed fluorescence emitters deposited by a single thermal evaporation step, suggesting that the efficiency of a light-emitting device with simplified structure can be high.

Electrically detected magnetic resonance and near-zero field magnetoresistance in 28Si/28SiO2

We report on electrically detected magnetic resonance (EDMR) and near-zero-field magnetoresistance (NZFMR) measurements observed through spin-dependent trap-assisted-tunneling on unpassivated Si/SiO2 metal–insulator–semiconductor capacitors comparing those containing silicon of natural isotopic abundance and silicon depleted of 29Si. Although our measurements involve monitoring the spin-dependence of the trap-assisted-tunneling current responsible for leakage across the oxide, the EDMR spectra resemble that of a combination of Pb0 and Pb1 silicon dangling bonds sites at the Si/SiO2 interface. Additionally, we observe a substantial narrowing of the NZFMR response with the removal of 29Si nuclei. The breadth of the NZFMR response is strongly influenced by hyperfine interactions. Since superhyerfine interactions between 29Si nuclei and silicon dangling bonds at the Si/SiO2 interface are a full order of magnitude stronger than such interactions involving silicon dangling bonds defects (E′ centers) within the oxide, the NZFMR results also strongly suggest a response dominated by Si/SiO2 interface trap defects. These results collectively suggest very strongly that the leakage currents that we observe involve tunneling from Si/SiO2 Pb dangling bonds to defects within the oxide. Our results thus offer fundamental insight into technologically important phenomena involving oxide leakage currents in metal–oxide–semiconductor devices such as stress induced leakage currents and time dependent dielectric breakdown.

Boron-Doped Diamond MOSFETs With High Output Current and Extrinsic Transconductance

Boron-doped diamond (B-diamond) metal–oxide–semiconductor (MOS) capacitor and MOS field-effect transistor (MOSFET) are fabricated on a flat diamond epitaxial layer. Their electrical properties and thermal stabilities after annealing at 500 °C are investigated. Annealing makes the leakage current density of the B-diamond MOS capacitor increase slightly. There is a larger stretch-out for the capacitance-voltage curve in the depletion region after annealing than that before annealing. The drain-current maxima for the as-fabricated and 500 °C-annealed MOSFETs are obtained as −0.49 and −0.60 mA/mm, respectively. Extrinsic transconductance maxima are 18.7 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$21.4~\mu \text{S}$ </tex-math></inline-formula> /mm, respectively. These obtained values are considerably larger than those obtained by the previously reported B-diamond MOSFETs.

Demonstration of TiO₂ Based Ultra High-k (k = 30) Metal-Insulator-Semiconductor Capacitor and Its Electrical Properties.

In this paper, we investigated TiO₂ as gate dielectric to achieve the large dielectric constant. The ultra high-k value over 30 was obtained by Capacitance-Voltage measurement of Al/Ti/TiO₂/Si Metal-Insulator-Semiconductor (MIS) capacitor. Among as deposited, rapid thermal annealing (RTA) at 750 °C and 1000 °C, the RTA at 750 °C showed the lowest gate leakage current. It implies that TiO₂ has optimum RTA temperature having the lowest leakage current. When TiO₂ is annealed at 750 °C, the phase of TiO₂ changes to anatase and interfacial layer between TiOx and Si was formed. While TiO₂ is annealed at 1000 °C, the phase of TiO₂ changes to rutile and diffusion of silicon atoms was clearly observed and it causes the silicide formation. Based on measurement data, we proposed the energy band diagram of Al/TiO₂/Si MIS capacitors. This diagram shows that the energy band gap of RTA at 750 °C is expanded while that of RTA at 1000 °C is contracted. In addition, TiO₂ with RTA at 550 °C was tested to confirm leakage current and it shows lower leakage current than RTA at 750 °C as we expected. This result confirmed that optimum RTA temperature of TiO₂ would exist under 750 °C.

Improved operational reliability of MOCVD-grown AlSiO gate dielectric on β-Ga2O3 (001) by post-metallization annealing

In this work, we studied the impact of post-metallization annealing (PMA) on interfacial and bulk dielectric properties of AlSiO/β-Ga2O3 metal–oxide–semiconductor capacitors (MOSCAPs). Annealing at 300 °C improved the reverse operational stability within the test operation range from −10 V to −42 V. The near-interface fast and slow traps were both suppressed by PMA at 300 °C and 350 °C, leading to a negligible flat-band voltage hysteresis. The low gate leakage region was extended from 3.7 MV cm−1 to 4 MV cm−1 and the breakdown strength was improved from 7.8 MV cm−1 to 8.2 MV cm−1 for AlSiO/β-Ga2O3 MOSCAPs with PMA at 300 °C compared with not-annealed samples. The superior operational reliability demonstrated in this work is useful for future high-performance and reliable MOS-based Ga2O3 transistors.