Self-timed Rings Research Articles

Efficient FPGA implementation of high-speed true random number generator.

High-speed true random number generator is a building block in the modern information security system. We propose and demonstrate an efficient high-speed true random number generator based on multiple parallel self-timed rings (STRs). To improve the security, we evaluate the randomness of the entropy source by min-entropy and exploit the information-theoretically provable Toeplitz-hashing extractor. To minimize the consumption of hardware resources of a field programmable gate array at a predetermined high throughput and maximize the throughput with the limited hardware resources, we systematically derive and investigate the dependence of the data throughput and the total consumed resources of the random number generator on the system parameters. On this basis, we make a joint optimization for the degree of parallelism of the STRs and the extraction efficiency of the extractor. A 10-Gbps true random number generator is implemented efficiently, so that the output random bits can pass all the National Institute of Standards and Technology (NIST) and Dieharder test suites.

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices

Oscillating rings are widely used in CMOS logic devices because they are easy to integrate, require low area and low power. Their main disadvantage is that they tend to lock to each other and/or to an external periodic signal. This locking phenomenon can render a system based on a freely running oscillator non-functional. A detailed study of the causes of the phenomenon and how to avoid it, is therefore of paramount importance. In this paper, we conduct a detailed examination of the locking phenomenon using the most commonly used rings: ring oscillators, transient effect ring oscillators, and self-timed rings. We then analyze the consequences of locking on different use cases based on oscillating rings and provide design recommendations to minimize its impact. Our results could help designers better anticipate locking phenomenon in their future designs. To ensure reproducibility of the results, the VHDL code of all the experiments is available and can be downloaded from a dedicated web page.

Evaluation and Monitoring of Free Running Oscillators Serving as Source of Randomness

In this paper, we evaluate clock signals generated in ring oscillators and self-timed rings and the way their jitter can be transformed into random numbers. We show that counting the periods of the jittery clock signal produces random numbers of significantly better quality than the methods in which the jittery signal is simply sampled (the case in almost all current methods). Moreover, we use the counter values to characterize and continuously monitor the source of randomness. However, instead of using the widely used statistical variance, we propose to use Allan variance to do so. There are two main advantages: Allan variance is insensitive to low frequency noises such as flicker noise that are known to be autocorrelated and significantly less circuitry is required for its computation than that used to compute commonly used variance. We also show that it is essential to use a differential principle of randomness extraction from the jitter based on the use of two identical oscillators to avoid autocorrelations originating from external and internal global jitter sources and that this fact is valid for both kinds of rings. Last but not least, we propose a method of statistical testing based on high order Markov model to show the reduced dependencies when the proposed randomness extraction is applied.

A New TRNG Based on Coherent Sampling With Self-Timed Rings

Random numbers play a key role in applications such as industrial simulations, laboratory experimentation, computer games, and engineering problem solving. The design of new true random generators (TRNGs) has attracted the attention of the research community for many years. Designs with little hardware requirements and high throughput are demanded by new and powerful applications. In this paper, we introduce the design of a novel TRNG based on the coherent sampling (CS) phenomenon. Contrary to most designs based on this phenomenon, ours uses self-timed rings (STRs) instead of the commonly employed ring oscillators (ROs). Our design has two key advantages over existing proposals based on CS. It does not depend on the FPGA vendor used and does not need manual placement and routing in the manufacturing process, resulting in a highly portable generator. Our experiments show that the TRNG offers a very high throughput with a moderate cost in hardware. The results obtained with ENT, DIEHARD, and National Institute of Standards and Technology (NIST) statistical test suites evidence that the output bitstream behaves as a truly random variable.

Constrained Asynchronous Ring Structures for Robust Digital Oscillators

On-chip digital oscillators are ubiquitous in every communication applications like in RF architectures or intra-chip communication systems. Actually, their integration to the standard CMOS design flow, their ability to generate high-frequency signals, as well as their configurability make them really attractive for designers. However, these kinds of digital oscillators suffer from their sensitivity to any process, voltage, or temperature variations. Self-timed systems are usually considered robust to these kinds of variations. This paper proposes the use of self-timed ring structures for generating high-resolution timing signals. One of the main difficulties when designing such oscillators is to avoid burst oscillating modes and produce uniformly spaced events in order to act as a periodic time-base. Based on a high-level ring model, enriched with stage switching timing information, the temporal behavior of oscillating self-timed rings is studied and their robustness to process variability is evaluated. Several ring architectures are explored to take advantage of complex combination of stages I/Os and it is shown that one can tune a tradeoff between oscillation period and signal stability. In addition, the paper provides designers with the ability to easily prevent burst oscillating modes by applying a very tractable ring design rule. Electrical simulations demonstrate the correctness and efficiency of the approach.

Performance analysis and optimisation of NCL self-timed rings

A self-timed ring using NULL convention logic (NCL) is presented. An analytical method to evaluate the speed of NCL rings has been developed. The analytical predictions are verified by a Synopsys simulation and excellent agreement between the theoretical predictions and simulation results is obtained. Some important principles for ring optimisation are obtained. The analysis leads to the speed optimisation of a 24-bit NCL divider.

A new asynchronous pipeline scheme: application to the design of a self-timed ring divider

This paper describes an efficient means of synchronizing and pipelining asynchronous circuits implemented using differential cascode voltage switch logic (DCVSL) precharged function blocks. A modified version of this logic, called LDCVSL (latch differential cascode voltage switch logic), which is similar to the LCDL (latched CMOS differential logic), or DCVSL with NORA-latch, is used to improve the storage capability of the precharged function blocks. Improving the storage capability of the building blocks allows the design of an efficient pipeline scheme which is described in detail. Following a description of its potential performance, the pipeline scheme is applied to the design of self-timed rings. It is shown that more compact ring structures can be obtained without loss of performance. Our design methodology is then presented. It is based on the use of a private asynchronous standard cell library, fully compatible with an existing CMOS standard cell library provided by the foundry. Our approach allows the rapid design of standard cell based asynchronous circuits. Finally, both the pipeline scheme and design approach are illustrated through the design of a 32-b self-timed ring divider. The division algorithm is first briefly presented. The chip architecture is then described with the results obtained after fabrication. The test chip has been fabricated using the CNET/SGS-Thomson 0.5 /spl mu/m three metal layer technology. The 0.7 mm/sup 2/ chip computes 32-b divisions in 101 ns with a power consumption of 30 mW at a throughput of 10 million operations per second.

Performance of iterative computation in self-timed rings

The computation of iterative functions need not be limited by the rate at which external signals, such as a clock, can be supplied to an on-chip circuit. Instead, self-timed structures can compute without clock or latch delays. In particular, a self-timed ring is a loop of logical stages that, after initialization with operands, computes multiple cycles of an iterative computation without further external handshaking. Viewed as a whole, a self-timed ring has a total latency and throughput dependent not only on the individual stages' latencies and cycle times, but also on the total number of stages, tokens, and extra “bubbles” in the ring. This article derives the performance characteristics of self-timed rings, illustrates them with graphs, and discusses the implications for designing rings with optimal performance. Certain suggested ring configurations allow iteration with no latches and zero delay overhead, achieving a total latency equal to just the sum of the raw function-block delays. This property has been verified by measurements on a chip that demonstrates a self-timed ring for the example function of floating-point division. Fabricated in 1.2Μ CMOS, the ring occupies 7 mm2 and generates a quotient bit every 2.8 ns.