Self-controllable Voltage Level Research Articles

Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1 V were 0.470 and 0.1923 V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively.At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37 V, whereas it decreased to 0.22 V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05 V when the Vt variability (= -6σ) was large, but the dvlp SRAM lowered it to 0.41 V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957 μW at VDD = 1.0 V, which was 9.46% of PST of the conv SRAM (10.12 μW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

PARAMETER ANALYSIS OF SRAM CIRCUIT

The study examined the different a number of power-saving strategies, including sleep, stack, sleep stack, transmission gate logic, or self-controllable voltage level- upper (SVL-U). These methods are used with SRAM cells that have 6 transistors (6T), 7 transistors (8T), 8 transistors (9T), and 10 transistors (10T). The SVL-U method and transmission gate logic are used in suggested SRAM cell. According to a comparison of SRAM memory array as well as cells, dynamic power is significantly decreased on average when compared to traditional methods. The 45nm and 90nm software applications from Cadence are also used for simulation. According to a thorough analysis of SRAM memory arrays and cells, PDP and EDP have, on average, been significantly decreased when contrasted the state-of-the- art hybrid VLSI techniques. Therefore, these SRAMs are suitable for extremely low power embedded structural appliances. Keywords: Semiconductor Memories, Memory organization, SRAM, Write operation, Read Operation.

Analysis of 7T SRAM Cell Based on MTCMOS, SVL and I-SVL Technique

Objective: To design and propose an optimized Volatile 7T based SRAM cell in terms of leakage currents and dynamic power. Methods: The methodology involved is Multi threshold Voltage CMOS (MTCMOS), Self Controllable Voltage Level (SVL) and Improved Self Controllable Voltage Level (I-SVL). Findings: The proposed work demonstrates that 7T based SRAM cell using I-SVL method is efficient in terms of leakage currents and dynamic power. Also, Comparative Leakage current and dynamic power analyses are done between MTCMOS, SVL, and I-SVL methods The Proposed work based on I-SVL is significant than the MTCMOS and SVL Technique. All the circuits are developed using the Cadence virtuoso tool and spectre simulator is used to carry out the simulation. Novelty: The paper proposes Low power Volatile Memory cell based on 7T with improvements in leakage and dynamic power values in comparison with the earlier literatures. The proposed I-SVL based cell is 89% and 85% efficient in terms of dynamic power in comparison with the earlier references. Keywords: Improved – Self Controllable Voltage Level (I-SVL); Improved Lower SVL (I-LSVL); Improved Upper SVL (I-USVL); Multi threshold Voltage CMOS(MTCMOS); Self Controllable Voltage Level (SVL); SRAM

Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique

As the technology is scaled the power consumption increases significantly, because of which the battery life of portable devices is reduced. Due to high power density, the increased power consumption becomes an obstacle for scaling of devices. Power optimization is the most significantly visible in future portable IC’s. As per increasing need for a low power circuit, the reduction in leakage current becomes very important aspect while designing any IC. The leakage can be reduced by altering the threshold voltage. Further as the technology is scaled FinFET is the alternate for CMOS with increased control of gate over the channel. In this paper a FinFET based 7T SRAM cell is proposed which is faster in its operation and consumes less power. In order to further reduce the leakage power, FinFET based 7T SRAM cell is designed using self-controllable voltage level (SVL) techniques. In this paper, an 18 nm FinFET based SRAM cell is designed using SVL circuit to reduce the leakage current and power. The proposed design has the least leakage current of 16.56 nA and leakage power of 11.59 nW by using the combined technique of LSVL and USVL. All the circuit design and simulation have been done in Cadence Virtuoso using 18 nM FinFET technology.

Dual-mode power reduction technique for real-time image and video processing board

In real-time image and video processing boards, power, speed, and area are the most often used measures for determining the performance of motion imagery applications. Due to technological advancement, power consumption has gained major attention in real-time image processing ability compared to speed. The increase in on-chip temperature due to larger power consumption has resulted in reduced operating life of chip and battery-driven devices. In this work, a new logic family has been introduced i.e., dual-mode logic (DML), which provides flexibility between the optimization of energy and delay (E-D optimization). This gate can be switched between two modes of operation that is a static mode (CMOS-like mode), which provides low power consumption and dynamic mode, which provides high speed. Recently, power leakage has become a dominant problem due to continuous data transfer among a large number of connected devices. Thus, to reduce power leakage, a self-controllable voltage level (SVL) power reduction technique is used along with DML logic. In the SVL technique, a maximum dc voltage is provided to the active load circuit on-demand or decrease the dc supplied to the load circuit in the standby mode. Integrating DML with the SVL technique reduces power consumption as well as leakage power. A 4-bit RCA, 8-bit RCA, and 16-bit RCA are used for verifying the proposed method and comparison of performance parameters is done with a conventional circuit. Complete circuit implementation and simulation are carried out in TANNER EDA version 13 tools with operating voltage of 1 V. The proposed system is further applied to real-time image, and we obtain the finest resolution level with minimum power consumption.

Design of Self Controllable Voltage Level Circuit SVL for Low Power and High Speed 12t Sram at 15nm Technology

Due to trend of decreasing the device Size and increase in the chip density, the complexity in design increased and it became very complex. The main factor which is main concern in this step is Power dissipation. This can be occurring in many forms like Dynamic, subthreshold leakage and Gate leakage. For every situation the designer has to try to reduce this Power Dissipation factor. In this paper we designed a low power 12T SRAM by using the 15nm technology. SRAMs have large number of applications in high speed registers, microprocessors, small memory banks, general computing applications etc. Therefore delay, power, speed, leakage current and stability are the main concerns. These parameters are in trade off to each other. This paper focuses on the leakage current, power and stability in 12T SRAM bit -cell. We introduce a circuit “self - controllable Voltage Level (SVL)” circuit. The main task of this circuit is to reduce the stand-by leakage power of 12T SRAM. In our Work, We are using the Cadence Virtuoso simulation tool for simulating our circuit. After Comparing our results to the previous methods used for reducing the power leakage we found that there is reduction in average power compare to the previous methods used for power reduction techniques.

Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

This article explains about the design of a new low power 11T SRAM cell. In this proposed method, two voltage sources are used, one is connected to the bit line and the other is connected to the bit bar line respectively in order to eliminate the swing voltage at the output nodes of the bit and bit bar lines. When the SRAM cell is in working mode the dynamic power dissipation is reduced by minimizing the swing voltage. Self-controllable voltage level is a technique in which PMOS transistor acts as a switch and NMOS transistors act as a resistors coupled in series reduces leakage current when the transistors change its state from sleep to active and vice versa. Reduce in leakage current causes the diminution in static power dissipation. To avoid the data retention difficulty, maximum voltage is supplied to the circuit during the active mode and reduced voltage is supplied during the stand-by mode. By using Synopsys EDA tool, all simulation results of power dissipation, delay, transistor utilization, power delay product and energy-delay product of the proposed 11T SRAM cell and other existing models of SRAM cell has been carried out in 30 nm CMOS technology.

Low power, high speed Schmitt trigger using SVL technique in nanoscale CMOS technology

Schmitt trigger device is mostly used in analogue and digital circuit as a wave-shaping device to resolve the noise problem, widely used to drive the load with fast switching low-power loss and low-power supply. Conventional Schmitt trigger provides more leakage power, so 4T Schmitt trigger overcomes this problem by using the Self-Controllable Voltage Level (SVL) techniques. The main purpose of this paper is to present the performance factor of Schmitt trigger by applying U-SVL and L-SVL and both technique. The simulation results perform in cadence tool and reported that static power (3.98 fW), dynamic power (38.04 pW), propagation delay (6.13 psec), hysteresis width (0.877 V), voltage gain (30.03 dB), periodic jitter (80 ns), frequency jitter (24.26 kHz), efficiency (63.06%), spectral power (5.388 aW), transconductance (7.17 × 10−14 S) and the total leakage power of individual transistors (1.17 pW) improve using both U-SVL and L-SVL techniques simultaneously with nanoscale measurement with supply voltage Vdd=0.7 V.

English

Memory is the most common part in CMOS applications. The power consumption and speed are important issue that has led to multiple designs with the purpose of minimizing the power during both read and write operations of SRAM .In modern high performance integrated circuits more than 40% of the total active mode energy is consumed due to leakage currents. The feature size of the transistor is scaled down the threshold voltages of MOSFETs have been reduced thereby increasing leakage power substantially. Leakage is the only source of energy consumption in an idle circuit .SRAM arrays are important sources of leakage since the majority of transistors are utilized for onchip memory in today‟s high performance microprocessors and systems-on-chips. A new leakage current reduction circuit called improved Self-controllable Voltage Level (SVL) circuit is developed and included to reduce the leakage power of 6T SRAM. Simulation result of 6T SRAM with improved SVL design using TANNER tool shows the reduction in total average power and delay.

Minimizing Power Consumption in CMOS Full Subtractor using SVL Technique

Full Subtractor using Self Controllable Voltage Level (SVL) Technique is designed in this paper. The circuit can supply an increased dc voltage to an active-load circuit required or can decrease the dc voltage supplied to a load circuit under standby mode is developed. Full Subtractor is a consumed low power and low Leakage as compare to conventional design with SVL technique. We may reduce the value of total power dissipation by applying the U-SVL (upper Self Controllable voltage level) technology in which the supply potential is increased and L-SVL (Lower Self Controllable voltage level) technology in which the ground potential is raised. The analysis paper represents how to control power using SVL techniques. The SVL technique based Full Subtractor compared to conventional design that based on power consumption, propagation delay speed and layout area is more preferred. Low-power techniques projected to reduce power in nanoscale CMOS-Very Large Scale Integration (VLSI) systems, Using SVL technique. The result shows that there is significant reduction in Power assimilation of Full Subtractor in reference mode. This design is much useful in designing the system that low power consumed. The circuit is designed using Cadence Tools in 45nm Technology.

English

English

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V th, channel length L and gate oxide thickness t ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.

Comparative Analysis of Self-Controllable Voltage Level (SVL) and Stacking Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45Nanometer Regime

Comparative Analysis of Self-Controllable Voltage Level (SVL) and Stacking Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45Nanometer Regime

A SRAM Memory Cell Design in FPGA

The main objective of this work is to design a memory cell in Field Programmable Gate Array (FPGA) that consumes lesser power with reduced delay constraint. In the existing system, the FPGA is based on 10T Static Random Access Memory (SRAM) cell configuration in which power consumption is relatively high. The proposed work includes a Self controllable Voltage Level (SVL) circuit along with 10T SRAM cell and asynchronous counters in read circuit memory block instead of shift registers. The stand-by leakage power of 10T SRAM is reduced by incorporating a newly-developed leakage current reduction circuit called SVL circuit, with minimal overheads in terms of chip area and speed, which retains data in standby mode. In asynchronous counters, external clock is connected to the clock input of the first flip-flop only, whereas the successive flip-flops change when it is triggered by the falling edge of the previous counterparts. The various FPGA components are implemented in 180nm technology to evaluate the FPGA performance. Parameters like average power consumption and power delay product are compared with the existing system and it is found that the proposed system consumes lesser power but at the cost of the power delay product. The software tool used for design and simulation of various FPGA components is TANNER S-Edit.

Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8 V, 75°C demonstrate power reduction by 59.4% in case of 1 bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1 bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45 V applied in active mode improves the maximum operating frequency by 16% in case of 1 bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode.

Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology

In this paper the impact of gate leakage on 7T static random access memory (SRAM) is described and three techniques for reducing gate leakage currents and sub threshold leakage currents are examined. In first technique, the supply voltage is decreased. In the second techniques the voltage of the ground node is increased. While in third technique the effective voltage across SRAM cell Vd = 0.348V and Vs = 0.234V are observed. In all the techniques the effective voltage across SRAM cell is decreased in stand-by mode using a dynamic self controllable voltage level (SVL) switch. Simulation results based on cadence tool for 45 nm technology show that the techniques in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node voltage is increased. Result obtained show that 437 FA reductions in the leakage currents of 7T SRAM can be achieved.

A low-leakage current power 45-nm CMOS SRAM

A low leakage power, 45-nm 1Kb SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a self-controllable voltage level (SVL) circuit was only 3.7 nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area.

A Large "Read" and "Write" Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM

We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, to achieve an expanded “read” and “write” margins and low leakage power in a 90-nm, 2-kbit, six-transistor CMOS SRAM. At the threshold voltage fluctuation of 6σ, the minimum supply voltage of the newly developed (dvlp.) SRAM for “write” operation was significantly reduced to 0.11V, less than half that of an equivalent conventional (conv.) SRAM. The standby leakage power of the dvlp. SRAM was only 1.17µW, which is 4.64% of that of the conv. SRAM at supply voltage of 1.0V. Moreover, the maximum operating clock frequency of the dvlp. SRAM was 138MHz, which is 15% higher than that (120MHz) of the conv. SRAM at VMM of 0.4V. An area overhead was 0.81% that of the conv. SRAM.

A self-controllable voltage level (svl) circuit and its low-power high-speed cmos circuit applications

A self-controllable voltage level (SVL) circuit which can supply a maximum dc voltage to an active-load circuit on request or can decrease the dc voltage supplied to a load circuit in standby mode was developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such circuits fitted with SVL circuits can retain data even in the standby mode. The standby power of an 8-bit 0.13-μm CMOS ripple carry adder (RCA) with an on-chip SVL circuit is 8.2 nW, namely, 4.0% of that of an equivalent conventional adder, while the output signal delay is 786 ps, namely, only 2.3% longer than that of the equivalent conventional adder. Moreover, the standby power of a 512-bit memory cell array incorporating an SVL circuit for a 0.13-μm 512-bit SRAM is 69.1 nW, which is 3.9% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-μm SRAM is 285 ps, that is, only 2 ps slower than that of the equivalent SRAM.