Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique

Abstract

As the technology is scaled the power consumption increases significantly, because of which the battery life of portable devices is reduced. Due to high power density, the increased power consumption becomes an obstacle for scaling of devices. Power optimization is the most significantly visible in future portable IC’s. As per increasing need for a low power circuit, the reduction in leakage current becomes very important aspect while designing any IC. The leakage can be reduced by altering the threshold voltage. Further as the technology is scaled FinFET is the alternate for CMOS with increased control of gate over the channel. In this paper a FinFET based 7T SRAM cell is proposed which is faster in its operation and consumes less power. In order to further reduce the leakage power, FinFET based 7T SRAM cell is designed using self-controllable voltage level (SVL) techniques. In this paper, an 18 nm FinFET based SRAM cell is designed using SVL circuit to reduce the leakage current and power. The proposed design has the least leakage current of 16.56 nA and leakage power of 11.59 nW by using the combined technique of LSVL and USVL. All the circuit design and simulation have been done in Cadence Virtuoso using 18 nM FinFET technology.