A SRAM Memory Cell Design in FPGA

Abstract

The main objective of this work is to design a memory cell in Field Programmable Gate Array (FPGA) that consumes lesser power with reduced delay constraint. In the existing system, the FPGA is based on 10T Static Random Access Memory (SRAM) cell configuration in which power consumption is relatively high. The proposed work includes a Self controllable Voltage Level (SVL) circuit along with 10T SRAM cell and asynchronous counters in read circuit memory block instead of shift registers. The stand-by leakage power of 10T SRAM is reduced by incorporating a newly-developed leakage current reduction circuit called SVL circuit, with minimal overheads in terms of chip area and speed, which retains data in standby mode. In asynchronous counters, external clock is connected to the clock input of the first flip-flop only, whereas the successive flip-flops change when it is triggered by the falling edge of the previous counterparts. The various FPGA components are implemented in 180nm technology to evaluate the FPGA performance. Parameters like average power consumption and power delay product are compared with the existing system and it is found that the proposed system consumes lesser power but at the cost of the power delay product. The software tool used for design and simulation of various FPGA components is TANNER S-Edit.